RTEMS 6.1
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Data Fields
CRYP_TypeDef Struct Reference
CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq

Crypto Processor. More...

#include <stm32h730xx.h>

Data Fields

__IO uint32_t CR
 
__IO uint32_t SR
 
__IO uint32_t DIN
 
__IO uint32_t DOUT
 
__IO uint32_t DMACR
 
__IO uint32_t IMSCR
 
__IO uint32_t RISR
 
__IO uint32_t MISR
 
__IO uint32_t K0LR
 
__IO uint32_t K0RR
 
__IO uint32_t K1LR
 
__IO uint32_t K1RR
 
__IO uint32_t K2LR
 
__IO uint32_t K2RR
 
__IO uint32_t K3LR
 
__IO uint32_t K3RR
 
__IO uint32_t IV0LR
 
__IO uint32_t IV0RR
 
__IO uint32_t IV1LR
 
__IO uint32_t IV1RR
 
__IO uint32_t CSGCMCCM0R
 
__IO uint32_t CSGCMCCM1R
 
__IO uint32_t CSGCMCCM2R
 
__IO uint32_t CSGCMCCM3R
 
__IO uint32_t CSGCMCCM4R
 
__IO uint32_t CSGCMCCM5R
 
__IO uint32_t CSGCMCCM6R
 
__IO uint32_t CSGCMCCM7R
 
__IO uint32_t CSGCM0R
 
__IO uint32_t CSGCM1R
 
__IO uint32_t CSGCM2R
 
__IO uint32_t CSGCM3R
 
__IO uint32_t CSGCM4R
 
__IO uint32_t CSGCM5R
 
__IO uint32_t CSGCM6R
 
__IO uint32_t CSGCM7R
 

Detailed Description

Crypto Processor.

Field Documentation

◆ CR

__IO uint32_t CRYP_TypeDef::CR

CRYP control register, Address offset: 0x00

◆ CSGCM0R

__IO uint32_t CRYP_TypeDef::CSGCM0R

CRYP GCM/GMAC context swap register 0, Address offset: 0x70

◆ CSGCM1R

__IO uint32_t CRYP_TypeDef::CSGCM1R

CRYP GCM/GMAC context swap register 1, Address offset: 0x74

◆ CSGCM2R

__IO uint32_t CRYP_TypeDef::CSGCM2R

CRYP GCM/GMAC context swap register 2, Address offset: 0x78

◆ CSGCM3R

__IO uint32_t CRYP_TypeDef::CSGCM3R

CRYP GCM/GMAC context swap register 3, Address offset: 0x7C

◆ CSGCM4R

__IO uint32_t CRYP_TypeDef::CSGCM4R

CRYP GCM/GMAC context swap register 4, Address offset: 0x80

◆ CSGCM5R

__IO uint32_t CRYP_TypeDef::CSGCM5R

CRYP GCM/GMAC context swap register 5, Address offset: 0x84

◆ CSGCM6R

__IO uint32_t CRYP_TypeDef::CSGCM6R

CRYP GCM/GMAC context swap register 6, Address offset: 0x88

◆ CSGCM7R

__IO uint32_t CRYP_TypeDef::CSGCM7R

CRYP GCM/GMAC context swap register 7, Address offset: 0x8C

◆ CSGCMCCM0R

__IO uint32_t CRYP_TypeDef::CSGCMCCM0R

CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50

◆ CSGCMCCM1R

__IO uint32_t CRYP_TypeDef::CSGCMCCM1R

CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54

◆ CSGCMCCM2R

__IO uint32_t CRYP_TypeDef::CSGCMCCM2R

CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58

◆ CSGCMCCM3R

__IO uint32_t CRYP_TypeDef::CSGCMCCM3R

CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C

◆ CSGCMCCM4R

__IO uint32_t CRYP_TypeDef::CSGCMCCM4R

CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60

◆ CSGCMCCM5R

__IO uint32_t CRYP_TypeDef::CSGCMCCM5R

CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64

◆ CSGCMCCM6R

__IO uint32_t CRYP_TypeDef::CSGCMCCM6R

CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68

◆ CSGCMCCM7R

__IO uint32_t CRYP_TypeDef::CSGCMCCM7R

CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C

◆ DIN

__IO uint32_t CRYP_TypeDef::DIN

CRYP data input register, Address offset: 0x08

◆ DMACR

__IO uint32_t CRYP_TypeDef::DMACR

CRYP DMA control register, Address offset: 0x10

◆ DOUT

__IO uint32_t CRYP_TypeDef::DOUT

CRYP data output register, Address offset: 0x0C

◆ IMSCR

__IO uint32_t CRYP_TypeDef::IMSCR

CRYP interrupt mask set/clear register, Address offset: 0x14

◆ IV0LR

__IO uint32_t CRYP_TypeDef::IV0LR

CRYP initialization vector left-word register 0, Address offset: 0x40

◆ IV0RR

__IO uint32_t CRYP_TypeDef::IV0RR

CRYP initialization vector right-word register 0, Address offset: 0x44

◆ IV1LR

__IO uint32_t CRYP_TypeDef::IV1LR

CRYP initialization vector left-word register 1, Address offset: 0x48

◆ IV1RR

__IO uint32_t CRYP_TypeDef::IV1RR

CRYP initialization vector right-word register 1, Address offset: 0x4C

◆ K0LR

__IO uint32_t CRYP_TypeDef::K0LR

CRYP key left register 0, Address offset: 0x20

◆ K0RR

__IO uint32_t CRYP_TypeDef::K0RR

CRYP key right register 0, Address offset: 0x24

◆ K1LR

__IO uint32_t CRYP_TypeDef::K1LR

CRYP key left register 1, Address offset: 0x28

◆ K1RR

__IO uint32_t CRYP_TypeDef::K1RR

CRYP key right register 1, Address offset: 0x2C

◆ K2LR

__IO uint32_t CRYP_TypeDef::K2LR

CRYP key left register 2, Address offset: 0x30

◆ K2RR

__IO uint32_t CRYP_TypeDef::K2RR

CRYP key right register 2, Address offset: 0x34

◆ K3LR

__IO uint32_t CRYP_TypeDef::K3LR

CRYP key left register 3, Address offset: 0x38

◆ K3RR

__IO uint32_t CRYP_TypeDef::K3RR

CRYP key right register 3, Address offset: 0x3C

◆ MISR

__IO uint32_t CRYP_TypeDef::MISR

CRYP masked interrupt status register, Address offset: 0x1C

◆ RISR

__IO uint32_t CRYP_TypeDef::RISR

CRYP raw interrupt status register, Address offset: 0x18

◆ SR

__IO uint32_t CRYP_TypeDef::SR

CRYP status register, Address offset: 0x04

The documentation for this struct was generated from the following files:
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