RTEMS 6.1
Loading...
Searching...
No Matches
Data Fields
ADC_TypeDef Struct Reference
CMSIS_Device » Stm32h723xx | CMSIS_Device » Stm32h725xx | CMSIS_Device » Stm32h730xx | CMSIS_Device » Stm32h730xxQ | CMSIS_Device » Stm32h733xx | CMSIS_Device » Stm32h735xx | CMSIS_Device » Stm32h742xx | CMSIS_Device » Stm32h743xx | CMSIS_Device » Stm32h745xg | CMSIS_Device » Stm32h745xx | CMSIS_Device » Stm32h747xg | CMSIS_Device » Stm32h747xx | CMSIS_Device » Stm32h750xx | CMSIS_Device » Stm32h753xx | CMSIS_Device » Stm32h755xx | CMSIS_Device » Stm32h757xx | CMSIS_Device » Stm32h7a3xx | CMSIS_Device » Stm32h7a3xxq | CMSIS_Device » Stm32h7b0xx | CMSIS_Device » Stm32h7b0xxQ | CMSIS_Device » Stm32h7b3xx | CMSIS_Device » Stm32h7b3xxq » Peripheral_registers_structures

Analog to Digital Converter. More...

#include <stm32h723xx.h>

Data Fields

__IO uint32_t ISR
 
__IO uint32_t IER
 
__IO uint32_t CR
 
__IO uint32_t CFGR
 
__IO uint32_t CFGR2
 
__IO uint32_t SMPR1
 
__IO uint32_t SMPR2
 
__IO uint32_t PCSEL_RES0
 
__IO uint32_t LTR1_TR1
 
__IO uint32_t HTR1_TR2
 
__IO uint32_t RES1_TR3
 
uint32_t RESERVED2
 
__IO uint32_t SQR1
 
__IO uint32_t SQR2
 
__IO uint32_t SQR3
 
__IO uint32_t SQR4
 
__IO uint32_t DR
 
uint32_t RESERVED3
 
uint32_t RESERVED4
 
__IO uint32_t JSQR
 
uint32_t RESERVED5 [4]
 
__IO uint32_t OFR1
 
__IO uint32_t OFR2
 
__IO uint32_t OFR3
 
__IO uint32_t OFR4
 
uint32_t RESERVED6 [4]
 
__IO uint32_t JDR1
 
__IO uint32_t JDR2
 
__IO uint32_t JDR3
 
__IO uint32_t JDR4
 
uint32_t RESERVED7 [4]
 
__IO uint32_t AWD2CR
 
__IO uint32_t AWD3CR
 
uint32_t RESERVED8
 
uint32_t RESERVED9
 
__IO uint32_t LTR2_DIFSEL
 
__IO uint32_t HTR2_CALFACT
 
__IO uint32_t LTR3_RES10
 
__IO uint32_t HTR3_RES11
 
__IO uint32_t DIFSEL_RES12
 
__IO uint32_t CALFACT_RES13
 
__IO uint32_t CALFACT2_RES14
 
__IO uint32_t PCSEL
 
__IO uint32_t LTR1
 
__IO uint32_t HTR1
 
uint32_t RESERVED1
 
__IO uint32_t LTR2
 
__IO uint32_t HTR2
 
__IO uint32_t LTR3
 
__IO uint32_t HTR3
 
__IO uint32_t DIFSEL
 
__IO uint32_t CALFACT
 
__IO uint32_t CALFACT2
 

Detailed Description

Analog to Digital Converter.

Field Documentation

◆ AWD2CR

__IO uint32_t ADC_TypeDef::AWD2CR

ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0

◆ AWD3CR

__IO uint32_t ADC_TypeDef::AWD3CR

ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4

◆ CALFACT

__IO uint32_t ADC_TypeDef::CALFACT

ADC Calibration Factors, Address offset: 0xC4

◆ CALFACT2

__IO uint32_t ADC_TypeDef::CALFACT2

ADC Linearity Calibration Factors, Address offset: 0xC8

◆ CALFACT2_RES14

__IO uint32_t ADC_TypeDef::CALFACT2_RES14

ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8

◆ CALFACT_RES13

__IO uint32_t ADC_TypeDef::CALFACT_RES13

ADC Calibration Factors specific ADC1/2, Address offset: 0xC4

◆ CFGR

__IO uint32_t ADC_TypeDef::CFGR

ADC Configuration register, Address offset: 0x0C

◆ CFGR2

__IO uint32_t ADC_TypeDef::CFGR2

ADC Configuration register 2, Address offset: 0x10

◆ CR

__IO uint32_t ADC_TypeDef::CR

ADC control register, Address offset: 0x08

◆ DIFSEL

__IO uint32_t ADC_TypeDef::DIFSEL

ADC Differential Mode Selection Register, Address offset: 0xC0

◆ DIFSEL_RES12

__IO uint32_t ADC_TypeDef::DIFSEL_RES12

ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0

◆ DR

__IO uint32_t ADC_TypeDef::DR

ADC regular data register, Address offset: 0x40

◆ HTR1

__IO uint32_t ADC_TypeDef::HTR1

ADC watchdog higher threshold register 1, Address offset: 0x24

◆ HTR1_TR2

__IO uint32_t ADC_TypeDef::HTR1_TR2

ADC watchdog higher threshold register 1, Address offset: 0x24

◆ HTR2

__IO uint32_t ADC_TypeDef::HTR2

ADC watchdog Higher threshold register 2, Address offset: 0xB4

◆ HTR2_CALFACT

__IO uint32_t ADC_TypeDef::HTR2_CALFACT

ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4

◆ HTR3

__IO uint32_t ADC_TypeDef::HTR3

ADC watchdog Higher threshold register 3, Address offset: 0xBC

◆ HTR3_RES11

__IO uint32_t ADC_TypeDef::HTR3_RES11

ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC

◆ IER

__IO uint32_t ADC_TypeDef::IER

ADC Interrupt Enable Register, Address offset: 0x04

◆ ISR

__IO uint32_t ADC_TypeDef::ISR

ADC Interrupt and Status Register, Address offset: 0x00

◆ JDR1

__IO uint32_t ADC_TypeDef::JDR1

ADC injected data register 1, Address offset: 0x80

◆ JDR2

__IO uint32_t ADC_TypeDef::JDR2

ADC injected data register 2, Address offset: 0x84

◆ JDR3

__IO uint32_t ADC_TypeDef::JDR3

ADC injected data register 3, Address offset: 0x88

◆ JDR4

__IO uint32_t ADC_TypeDef::JDR4

ADC injected data register 4, Address offset: 0x8C

◆ JSQR

__IO uint32_t ADC_TypeDef::JSQR

ADC injected sequence register, Address offset: 0x4C

◆ LTR1

__IO uint32_t ADC_TypeDef::LTR1

ADC watchdog Lower threshold register 1, Address offset: 0x20

◆ LTR1_TR1

__IO uint32_t ADC_TypeDef::LTR1_TR1

ADC watchdog Lower threshold register 1, Address offset: 0x20

◆ LTR2

__IO uint32_t ADC_TypeDef::LTR2

ADC watchdog Lower threshold register 2, Address offset: 0xB0

◆ LTR2_DIFSEL

__IO uint32_t ADC_TypeDef::LTR2_DIFSEL

ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0

◆ LTR3

__IO uint32_t ADC_TypeDef::LTR3

ADC watchdog Lower threshold register 3, Address offset: 0xB8

◆ LTR3_RES10

__IO uint32_t ADC_TypeDef::LTR3_RES10

ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8

◆ OFR1

__IO uint32_t ADC_TypeDef::OFR1

ADC offset register 1, Address offset: 0x60

◆ OFR2

__IO uint32_t ADC_TypeDef::OFR2

ADC offset register 2, Address offset: 0x64

◆ OFR3

__IO uint32_t ADC_TypeDef::OFR3

ADC offset register 3, Address offset: 0x68

◆ OFR4

__IO uint32_t ADC_TypeDef::OFR4

ADC offset register 4, Address offset: 0x6C

◆ PCSEL

__IO uint32_t ADC_TypeDef::PCSEL

ADC pre-channel selection, Address offset: 0x1C

◆ PCSEL_RES0

__IO uint32_t ADC_TypeDef::PCSEL_RES0

Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C

◆ RES1_TR3

__IO uint32_t ADC_TypeDef::RES1_TR3

Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28

◆ RESERVED1

uint32_t ADC_TypeDef::RESERVED1

Reserved, 0x028

◆ RESERVED2

uint32_t ADC_TypeDef::RESERVED2

Reserved, 0x02C

◆ RESERVED3

uint32_t ADC_TypeDef::RESERVED3

Reserved, 0x044

◆ RESERVED4

uint32_t ADC_TypeDef::RESERVED4

Reserved, 0x048

◆ RESERVED5

uint32_t ADC_TypeDef::RESERVED5

Reserved, 0x050 - 0x05C

◆ RESERVED6

uint32_t ADC_TypeDef::RESERVED6

Reserved, 0x070 - 0x07C

◆ RESERVED7

uint32_t ADC_TypeDef::RESERVED7

Reserved, 0x090 - 0x09C

◆ RESERVED8

uint32_t ADC_TypeDef::RESERVED8

Reserved, 0x0A8

◆ RESERVED9

uint32_t ADC_TypeDef::RESERVED9

Reserved, 0x0AC

◆ SMPR1

__IO uint32_t ADC_TypeDef::SMPR1

ADC sample time register 1, Address offset: 0x14

◆ SMPR2

__IO uint32_t ADC_TypeDef::SMPR2

ADC sample time register 2, Address offset: 0x18

◆ SQR1

__IO uint32_t ADC_TypeDef::SQR1

ADC regular sequence register 1, Address offset: 0x30

◆ SQR2

__IO uint32_t ADC_TypeDef::SQR2

ADC regular sequence register 2, Address offset: 0x34

◆ SQR3

__IO uint32_t ADC_TypeDef::SQR3

ADC regular sequence register 3, Address offset: 0x38

◆ SQR4

__IO uint32_t ADC_TypeDef::SQR4

ADC regular sequence register 4, Address offset: 0x3C

The documentation for this struct was generated from the following files:
Generated by doxygen 1.9.6