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RTEMS 6.1
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Macros | |
| #define | WWDG_PRESCALER_1 0x00000000u |
| #define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 |
| #define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 |
| #define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) |
| #define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 |
| #define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) |
| #define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) |
| #define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB |
| #define WWDG_PRESCALER_1 0x00000000u |
WWDG counter clock = (PCLK1/4096)/1
| #define WWDG_PRESCALER_128 WWDG_CFR_WDGTB |
WWDG counter clock = (PCLK1/4096)/128
| #define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 |
WWDG counter clock = (PCLK1/4096)/16
| #define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 |
WWDG counter clock = (PCLK1/4096)/2
| #define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) |
WWDG counter clock = (PCLK1/4096)/32
| #define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 |
WWDG counter clock = (PCLK1/4096)/4
| #define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) |
WWDG counter clock = (PCLK1/4096)/64
| #define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) |
WWDG counter clock = (PCLK1/4096)/8