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RTEMS 6.1
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Functions | |
| int32_t | MT25TL01G_GetFlashInfo (MT25TL01G_Info_t *pInfo) |
| Return the configuration of the QSPI memory. | |
| int32_t | MT25TL01G_Enter4BytesAddressMode (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| This function set the QSPI memory in 4-byte address mode SPI/QPI; 1-0-1/4-0-4. | |
| int32_t | MT25TL01G_Exit4BytesAddressMode (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Flash exit 4 Byte address mode. Effect 3/4 address byte commands only. SPI/QPI; 1-0-0/4-0-0. | |
| int32_t | MT25TL01G_AutoPollingMemReady (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Polling WIP(Write In Progress) bit become to 0 SPI/QPI;4-0-4. | |
| int32_t | MT25TL01G_WriteEnable (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| This function send a Write Enable and wait it is effective. | |
| int32_t | MT25TL01G_WriteDisable (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| This function reset the (WEL) Write Enable Latch bit. SPI/QPI; 1-0-0/4-0-0. | |
| int32_t | MT25TL01G_PageProgram (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t WriteAddr, uint32_t Size) |
| Writes an amount of data to the QSPI memory. SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4. | |
| int32_t | MT25TL01G_ReadDTR (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t ReadAddr, uint32_t Size) |
| Reads an amount of data from the QSPI memory on DTR mode. SPI/QPI; 1-1-1/1-1-2/1-4-4/4-4-4. | |
| int32_t | MT25TL01G_ReadSTR (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t ReadAddr, uint32_t Size) |
| Reads an amount of data from the QSPI memory on STR mode. SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4. | |
| int32_t | MT25TL01G_BlockErase (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint32_t BlockAddress, MT25TL01G_Erase_t BlockSize) |
| Erases the specified block of the QSPI memory. MT25TL01G support 4K, 32K, 64K size block erase commands. SPI/QPI; 1-1-0/4-4-0. | |
| int32_t | MT25TL01G_ChipErase (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Whole chip erase. SPI/QPI; 1-0-0/4-0-0. | |
| int32_t | MT25TL01G_ReadStatusRegister (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *Value) |
| Read Flash Status register value SPI/QPI; 1-0-1/4-0-4. | |
| int32_t | MT25TL01G_EnterQPIMode (QSPI_HandleTypeDef *Ctx) |
| This function put QSPI memory in QPI mode (Quad I/O) from SPI mode. SPI -> QPI; 1-x-x -> 4-4-4 SPI; 1-0-0. | |
| int32_t | MT25TL01G_ExitQPIMode (QSPI_HandleTypeDef *Ctx) |
| This function put QSPI memory in SPI mode (Single I/O) from QPI mode. QPI -> SPI; 4-4-4 -> 1-x-x QPI; 4-0-0. | |
| int32_t | MT25TL01G_EnableMemoryMappedModeDTR (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Reads an amount of data from the QSPI memory on DTR mode. SPI/QPI; 1-1-1/1-1-2/1-4-4/4-4-4. | |
| int32_t | MT25TL01G_EnableMemoryMappedModeSTR (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Reads an amount of data from the QSPI memory on STR mode. SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4. | |
| int32_t | MT25TL01G_ResetEnable (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Flash reset enable command SPI/QPI; 1-0-0, 4-0-0. | |
| int32_t | MT25TL01G_ResetMemory (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Flash reset memory command SPI/QPI; 1-0-0, 4-0-0. | |
| int32_t | MT25TL01G_ReadID (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *ID) |
| Read Flash 3 Byte IDs. Manufacturer ID, Memory type, Memory density SPI/QPI; 1-0-1/4-0-4. | |
| int32_t | MT25TL01G_ProgEraseSuspend (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Program/Erases suspend. Interruption Program/Erase operations. After the device has entered Erase-Suspended mode, system can read any address except the block/sector being Program/Erased. SPI/QPI; 1-0-0/4-0-0. | |
| int32_t | MT25TL01G_ProgEraseResume (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Program/Erases resume. SPI/QPI; 1-0-0/4-0-0. | |
| int32_t | MT25TL01G_EnterDeepPowerDown (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Deep power down. The device is not active and all Write/Program/Erase instruction are ignored. SPI/QPI; 1-0-0/4-0-0. | |
| int32_t | MT25TL01G_ReleaseFromDeepPowerDown (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode) |
| Release from deep power down. After CS# go high, system need wait tRES1 time for device ready. SPI/QPI; 1-0-0/4-0-0. | |
| int32_t | MT25TL01G_ReadSPBLockRegister (QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *SPBRegister) |
| Read SECTOR PROTECTION Block register value. SPI; 1-0-1. | |
| int32_t MT25TL01G_AutoPollingMemReady | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Polling WIP(Write In Progress) bit become to 0 SPI/QPI;4-0-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_BlockErase | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode, | ||
| uint32_t | BlockAddress, | ||
| MT25TL01G_Erase_t | BlockSize | ||
| ) |
Erases the specified block of the QSPI memory. MT25TL01G support 4K, 32K, 64K size block erase commands. SPI/QPI; 1-1-0/4-4-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| BlockAddress | Block address to erase |
| QSPI | memory status |
| int32_t MT25TL01G_ChipErase | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Whole chip erase. SPI/QPI; 1-0-0/4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_EnableMemoryMappedModeDTR | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Reads an amount of data from the QSPI memory on DTR mode. SPI/QPI; 1-1-1/1-1-2/1-4-4/4-4-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_EnableMemoryMappedModeSTR | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Reads an amount of data from the QSPI memory on STR mode. SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_Enter4BytesAddressMode | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
This function set the QSPI memory in 4-byte address mode SPI/QPI; 1-0-1/4-0-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_EnterDeepPowerDown | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Deep power down. The device is not active and all Write/Program/Erase instruction are ignored. SPI/QPI; 1-0-0/4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_EnterQPIMode | ( | QSPI_HandleTypeDef * | Ctx | ) |
This function put QSPI memory in QPI mode (Quad I/O) from SPI mode. SPI -> QPI; 1-x-x -> 4-4-4 SPI; 1-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_Exit4BytesAddressMode | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Flash exit 4 Byte address mode. Effect 3/4 address byte commands only. SPI/QPI; 1-0-0/4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_ExitQPIMode | ( | QSPI_HandleTypeDef * | Ctx | ) |
This function put QSPI memory in SPI mode (Single I/O) from QPI mode. QPI -> SPI; 4-4-4 -> 1-x-x QPI; 4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_GetFlashInfo | ( | MT25TL01G_Info_t * | pInfo | ) |
Return the configuration of the QSPI memory.
| pInfo | pointer on the configuration structure |
| QSPI | memory status |
| int32_t MT25TL01G_PageProgram | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode, | ||
| uint8_t * | pData, | ||
| uint32_t | WriteAddr, | ||
| uint32_t | Size | ||
| ) |
Writes an amount of data to the QSPI memory. SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| pData | Pointer to data to be written |
| WriteAddr | Write start address |
| Size | Size of data to write. Range 1 ~ 256 |
| QSPI | memory status |
| int32_t MT25TL01G_ProgEraseResume | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Program/Erases resume. SPI/QPI; 1-0-0/4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_ProgEraseSuspend | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Program/Erases suspend. Interruption Program/Erase operations. After the device has entered Erase-Suspended mode, system can read any address except the block/sector being Program/Erased. SPI/QPI; 1-0-0/4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_ReadDTR | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode, | ||
| uint8_t * | pData, | ||
| uint32_t | ReadAddr, | ||
| uint32_t | Size | ||
| ) |
Reads an amount of data from the QSPI memory on DTR mode. SPI/QPI; 1-1-1/1-1-2/1-4-4/4-4-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| pData | Pointer to data to be read |
| ReadAddr | Read start address |
| Size | Size of data to read |
| QSPI | memory status |
| int32_t MT25TL01G_ReadID | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode, | ||
| uint8_t * | ID | ||
| ) |
Read Flash 3 Byte IDs. Manufacturer ID, Memory type, Memory density SPI/QPI; 1-0-1/4-0-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| ID | pointer to flash id value |
| QSPI | memory status |
| int32_t MT25TL01G_ReadSPBLockRegister | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode, | ||
| uint8_t * | SPBRegister | ||
| ) |
Read SECTOR PROTECTION Block register value. SPI; 1-0-1.
| Ctx | Component object pointer |
| Mode | Interface mode |
| SPBRegister | pointer to SPBRegister value |
| QSPI | memory status |
| int32_t MT25TL01G_ReadStatusRegister | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode, | ||
| uint8_t * | Value | ||
| ) |
Read Flash Status register value SPI/QPI; 1-0-1/4-0-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| Value | pointer to status register value |
| QSPI | memory status |
| int32_t MT25TL01G_ReadSTR | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode, | ||
| uint8_t * | pData, | ||
| uint32_t | ReadAddr, | ||
| uint32_t | Size | ||
| ) |
Reads an amount of data from the QSPI memory on STR mode. SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4.
| Ctx | Component object pointer |
| Mode | Interface mode |
| pData | Pointer to data to be read |
| ReadAddr | Read start address |
| Size | Size of data to read |
| QSPI | memory status |
| int32_t MT25TL01G_ReleaseFromDeepPowerDown | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Release from deep power down. After CS# go high, system need wait tRES1 time for device ready. SPI/QPI; 1-0-0/4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_ResetEnable | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Flash reset enable command SPI/QPI; 1-0-0, 4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_ResetMemory | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
Flash reset memory command SPI/QPI; 1-0-0, 4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_WriteDisable | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
This function reset the (WEL) Write Enable Latch bit. SPI/QPI; 1-0-0/4-0-0.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |
| int32_t MT25TL01G_WriteEnable | ( | QSPI_HandleTypeDef * | Ctx, |
| MT25TL01G_Interface_t | Mode | ||
| ) |
This function send a Write Enable and wait it is effective.
| Ctx | Component object pointer |
| Mode | Interface mode |
| QSPI | memory status |