Configuration_section_for_CMSIS

Macros
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	SMPS
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	SMPS
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	SMPS
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	__CM7_REV   0x0101U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	__CM7_REV   0x0101U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	DUAL_CORE
#define	SMPS
#define	DUAL_CORE
#define	SMPS
#define	DUAL_CORE
#define	SMPS
#define	DUAL_CORE
#define	SMPS
#define	__CM7_REV   0x0101U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	__CM7_REV   0x0101U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	DUAL_CORE
#define	SMPS
#define	DUAL_CORE
#define	SMPS
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	SMPS
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	SMPS
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U
#define	SMPS
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
#define	__NVIC_PRIO_BITS   4U
#define	__Vendor_SysTickConfig   0U
#define	__FPU_PRESENT   1U
#define	__ICACHE_PRESENT   1U
#define	__DCACHE_PRESENT   1U

Detailed Description

Macro Definition Documentation

__CM7_REV [1/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [2/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [3/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [4/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [5/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [6/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [7/16]

#define __CM7_REV   0x0101U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p1

__CM7_REV [8/16]

#define __CM7_REV   0x0101U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p1

__CM7_REV [9/16]

#define __CM7_REV   0x0101U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p1

__CM7_REV [10/16]

#define __CM7_REV   0x0101U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p1

__CM7_REV [11/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [12/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [13/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [14/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [15/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__CM7_REV [16/16]

#define __CM7_REV   0x0110U

Configuration of the Cortex-M7 Processor and Core Peripherals.

Cortex-M7 revision r1p2

__DCACHE_PRESENT [1/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [2/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [3/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [4/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [5/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [6/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [7/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [8/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [9/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [10/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [11/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [12/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [13/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [14/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [15/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__DCACHE_PRESENT [16/16]

#define __DCACHE_PRESENT   1U

CM7 data cache present
Cortex-M7 processor and core peripherals

__FPU_PRESENT [1/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [2/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [3/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [4/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [5/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [6/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [7/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [8/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [9/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [10/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [11/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [12/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [13/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [14/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [15/16]

#define __FPU_PRESENT   1U

FPU present

__FPU_PRESENT [16/16]

#define __FPU_PRESENT   1U

FPU present

__ICACHE_PRESENT [1/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [2/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [3/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [4/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [5/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [6/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [7/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [8/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [9/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [10/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [11/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [12/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [13/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [14/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [15/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__ICACHE_PRESENT [16/16]

#define __ICACHE_PRESENT   1U

CM7 instruction cache present

__MPU_PRESENT [1/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [2/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [3/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [4/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [5/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [6/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [7/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [8/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [9/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [10/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [11/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [12/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [13/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [14/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [15/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__MPU_PRESENT [16/16]

#define __MPU_PRESENT   1U

CM7 provides an MPU

__NVIC_PRIO_BITS [1/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [2/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [3/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [4/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [5/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [6/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [7/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [8/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [9/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [10/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [11/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [12/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [13/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [14/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [15/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__NVIC_PRIO_BITS [16/16]

#define __NVIC_PRIO_BITS   4U

CM7 uses 4 Bits for the Priority Levels

__Vendor_SysTickConfig [1/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [2/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [3/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [4/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [5/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [6/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [7/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [8/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [9/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [10/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [11/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [12/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [13/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [14/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [15/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

__Vendor_SysTickConfig [16/16]

#define __Vendor_SysTickConfig   0U

Set to 1 if different SysTick Config is used

DUAL_CORE [1/6]

#define DUAL_CORE

Dual core line feature

DUAL_CORE [2/6]

#define DUAL_CORE

Dual core line feature

DUAL_CORE [3/6]

#define DUAL_CORE

Dual core line feature

DUAL_CORE [4/6]

#define DUAL_CORE

Dual core line feature

DUAL_CORE [5/6]

#define DUAL_CORE

Dual core line feature

DUAL_CORE [6/6]

#define DUAL_CORE

Dual core line feature

SMPS [1/12]

#define SMPS

Switched mode power supply feature

SMPS [2/12]

#define SMPS

Switched mode power supply feature

SMPS [3/12]

#define SMPS

Switched mode power supply feature

SMPS [4/12]

#define SMPS

Switched mode power supply feature

SMPS [5/12]

#define SMPS

Switched mode power supply feature

SMPS [6/12]

#define SMPS

Switched mode power supply feature

SMPS [7/12]

#define SMPS

Switched mode power supply feature

SMPS [8/12]

#define SMPS

Switched mode power supply feature

SMPS [9/12]

#define SMPS

Switched mode power supply feature

SMPS [10/12]

#define SMPS

Switched mode power supply feature

SMPS [11/12]

#define SMPS

Switched mode power supply feature

SMPS [12/12]

#define SMPS

Switched mode power supply feature