ADC common - Clock source

Macros
#define	ADC_CLOCK_SYNC_PCLK_DIV1   (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define	ADC_CLOCK_SYNC_PCLK_DIV2   (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define	ADC_CLOCK_SYNC_PCLK_DIV4   (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define	ADC_CLOCK_ASYNC_DIV1   (LL_ADC_CLOCK_ASYNC_DIV1)
#define	ADC_CLOCK_ASYNC_DIV2   (LL_ADC_CLOCK_ASYNC_DIV2)
#define	ADC_CLOCK_ASYNC_DIV4   (LL_ADC_CLOCK_ASYNC_DIV4)
#define	ADC_CLOCK_ASYNC_DIV6   (LL_ADC_CLOCK_ASYNC_DIV6)
#define	ADC_CLOCK_ASYNC_DIV8   (LL_ADC_CLOCK_ASYNC_DIV8)
#define	ADC_CLOCK_ASYNC_DIV10   (LL_ADC_CLOCK_ASYNC_DIV10)
#define	ADC_CLOCK_ASYNC_DIV12   (LL_ADC_CLOCK_ASYNC_DIV12)
#define	ADC_CLOCK_ASYNC_DIV16   (LL_ADC_CLOCK_ASYNC_DIV16)
#define	ADC_CLOCK_ASYNC_DIV32   (LL_ADC_CLOCK_ASYNC_DIV32)
#define	ADC_CLOCK_ASYNC_DIV64   (LL_ADC_CLOCK_ASYNC_DIV64)
#define	ADC_CLOCK_ASYNC_DIV128   (LL_ADC_CLOCK_ASYNC_DIV128)
#define	ADC_CLOCK_ASYNC_DIV256   (LL_ADC_CLOCK_ASYNC_DIV256)

Detailed Description

Macro Definition Documentation

ADC_CLOCK_ASYNC_DIV1

#define ADC_CLOCK_ASYNC_DIV1   (LL_ADC_CLOCK_ASYNC_DIV1)

ADC asynchronous clock without prescaler

ADC_CLOCK_ASYNC_DIV10

#define ADC_CLOCK_ASYNC_DIV10   (LL_ADC_CLOCK_ASYNC_DIV10)

ADC asynchronous clock with prescaler division by 10

ADC_CLOCK_ASYNC_DIV12

#define ADC_CLOCK_ASYNC_DIV12   (LL_ADC_CLOCK_ASYNC_DIV12)

ADC asynchronous clock with prescaler division by 12

ADC_CLOCK_ASYNC_DIV128

#define ADC_CLOCK_ASYNC_DIV128   (LL_ADC_CLOCK_ASYNC_DIV128)

ADC asynchronous clock with prescaler division by 128

ADC_CLOCK_ASYNC_DIV16

#define ADC_CLOCK_ASYNC_DIV16   (LL_ADC_CLOCK_ASYNC_DIV16)

ADC asynchronous clock with prescaler division by 16

ADC_CLOCK_ASYNC_DIV2

#define ADC_CLOCK_ASYNC_DIV2   (LL_ADC_CLOCK_ASYNC_DIV2)

ADC asynchronous clock with prescaler division by 2

ADC_CLOCK_ASYNC_DIV256

#define ADC_CLOCK_ASYNC_DIV256   (LL_ADC_CLOCK_ASYNC_DIV256)

ADC asynchronous clock with prescaler division by 256

ADC_CLOCK_ASYNC_DIV32

#define ADC_CLOCK_ASYNC_DIV32   (LL_ADC_CLOCK_ASYNC_DIV32)

ADC asynchronous clock with prescaler division by 32

ADC_CLOCK_ASYNC_DIV4

#define ADC_CLOCK_ASYNC_DIV4   (LL_ADC_CLOCK_ASYNC_DIV4)

ADC asynchronous clock with prescaler division by 4

ADC_CLOCK_ASYNC_DIV6

#define ADC_CLOCK_ASYNC_DIV6   (LL_ADC_CLOCK_ASYNC_DIV6)

ADC asynchronous clock with prescaler division by 6

ADC_CLOCK_ASYNC_DIV64

#define ADC_CLOCK_ASYNC_DIV64   (LL_ADC_CLOCK_ASYNC_DIV64)

ADC asynchronous clock with prescaler division by 64

ADC_CLOCK_ASYNC_DIV8

#define ADC_CLOCK_ASYNC_DIV8   (LL_ADC_CLOCK_ASYNC_DIV8)

ADC asynchronous clock with prescaler division by 8

ADC_CLOCK_SYNC_PCLK_DIV1

#define ADC_CLOCK_SYNC_PCLK_DIV1   (LL_ADC_CLOCK_SYNC_PCLK_DIV1)

ADC synchronous clock derived from AHB clock without prescaler

ADC_CLOCK_SYNC_PCLK_DIV2

#define ADC_CLOCK_SYNC_PCLK_DIV2   (LL_ADC_CLOCK_SYNC_PCLK_DIV2)

ADC synchronous clock derived from AHB clock with prescaler division by 2

ADC_CLOCK_SYNC_PCLK_DIV4

#define ADC_CLOCK_SYNC_PCLK_DIV4   (LL_ADC_CLOCK_SYNC_PCLK_DIV4)

ADC synchronous clock derived from AHB clock with prescaler division by 4