![]() |
RTEMS 5.2
|
Implementations for interrupt mechanisms for Time Test 27. More...
Go to the source code of this file.
Macros | |
#define | ERC32_BSP_USE_SYNCHRONOUS_TRAP 0 |
#define | TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1 |
#define | TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1) |
#define | TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) |
#define | TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) |
#define | MUST_WAIT_FOR_INTERRUPT 1 |
#define | Install_tm27_vector(handler) |
#define | Cause_tm27_intr() |
#define | Clear_tm27_intr() ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE ) |
#define | Lower_tm27_intr() /* empty */ |
Implementations for interrupt mechanisms for Time Test 27.
#define Cause_tm27_intr | ( | void | ) |
#define Install_tm27_vector | ( | handler | ) |