RTEMS 5.2
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fsl-mpc551x.h
1/*
2 * Modifications of the original file provided by Freescale are:
3 *
4 * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
5 *
6 * embedded brains GmbH
7 * Obere Lagerstr. 30
8 * 82178 Puchheim
9 * Germany
10 * <info@embedded-brains.de>
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/**************************************************************************/
35/* FILE NAME: mpc5510.h COPYRIGHT (c) Freescale 2008 */
36/* REVISION: 2.2 All Rights Reserved */
37/* */
38/* DESCRIPTION: */
39/* This file contain all of the register and bit field definitions for */
40/* MPC5510. */
41/**************************************************************************/
42/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
43
44/*************************************************/
45/* Example register & bit field write: */
46/* */
47/* <MODULE>.<REGISTER>.B.<BIT> = 1; */
48/* <MODULE>.<REGISTER>.R = 0x10000000; */
49/* */
50/*************************************************/
51
52#ifndef _MPC5510_H_
53#define _MPC5510_H_
54
55#ifndef ASM
56
57#include <stdint.h>
58
59#include <mpc55xx/regs-edma.h>
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65#ifdef __MWERKS__
66#pragma push
67#pragma ANSI_strict off
68#endif
69
70/****************************************************************************/
71/* MODULE : CRP */
72/****************************************************************************/
73 struct CRP_tag {
74
75 union {
76 uint32_t R;
77 struct {
78 uint32_t:12;
79 uint32_t IRC32KEN:1;
80 uint32_t XOSCEN:1;
81 uint32_t:1;
82 uint32_t OSC32KEN:1;
83 uint32_t TRIM32IRC:8;
84 uint32_t TRIMIRC:8;
85 } B;
86 } CLKSRC; /* Clock Source Register */
87
88 uint32_t crp_reserved1[3];
89
90 union {
91 uint32_t R;
92 struct {
93 uint32_t CNTEN:1;
94 uint32_t RTCIE:1;
95 uint32_t RTCF:1;
96 uint32_t ROVRF:1;
97 uint32_t RTCVAL:12;
98 uint32_t APIEN:1;
99 uint32_t APIIE:1;
100 uint32_t APIF:1;
101 uint32_t CLKSEL:2;
102 uint32_t ROVREN:1;
103 uint32_t APIVAL:10;
104 } B;
105 } RTCSC; /* RTC Status and Control Register */
106
107 union {
108 uint32_t R;
109 struct {
110 uint32_t RTCCNT:32;
111 } B;
112 } RTCCNT; /* RTC Counter Register */
113
114 uint32_t crp_reserved2[10];
115
116 union {
117 uint32_t R;
118 struct {
119 uint32_t:1;
120 uint32_t WKPSEL7:3;
121 uint32_t:1;
122 uint32_t WKPSEL6:3;
123 uint32_t:1;
124 uint32_t WKPSEL5:3;
125 uint32_t:1;
126 uint32_t WKPSEL4:3;
127 uint32_t:1;
128 uint32_t WKPSEL3:3;
129 uint32_t:1;
130 uint32_t WKPSEL2:3;
131 uint32_t:1;
132 uint32_t WKPSEL1:3;
133 uint32_t:1;
134 uint32_t WKPSEL0:3;
135 } B;
136 } WKPINSEL; /* Wakeup Pin Source Select Register */
137
138 union {
139 uint32_t R;
140 struct {
141 uint32_t WKPDET7:2;
142 uint32_t WKPDET6:2;
143 uint32_t WKPDET5:2;
144 uint32_t WKPDET4:2;
145 uint32_t WKPDET3:2;
146 uint32_t WKPDET2:2;
147 uint32_t WKPDET1:2;
148 uint32_t WKPDET0:2;
149 uint32_t:5;
150 uint32_t RTCOVREN:1;
151 uint32_t RTCWKEN:1;
152 uint32_t APIWKEN:1;
153 uint32_t:7;
154 uint32_t WKCLKSEL:1;
155 } B;
156 } WKSE; /* Wakeup Source Enable Register */
157
158 uint32_t crp_reserved3[2];
159
160 union {
161 uint32_t R;
162 struct {
163 uint32_t Z1VEC:30;
164 uint32_t Z1RST:1;
165 uint32_t VLE:1;
166 } B;
167 } Z1VEC; /* Z1 Reset Vector Register */
168
169 union {
170 uint32_t R;
171 struct {
172 uint32_t Z0VEC:30;
173 uint32_t Z0RST:1;
174 uint32_t:1;
175 } B;
176 } Z0VEC; /* Z0 Reset Vector Register */
177
178 union {
179 uint32_t R;
180 struct {
181 uint32_t RECPTR:30;
182 uint32_t FASTREC:1;
183 uint32_t:1;
184 } B;
185 } RECPTR; /* Reset Recovery Pointer Register */
186
187 uint32_t crp_reserved4;
188
189 union {
190 uint32_t R;
191 struct {
192 uint32_t SLEEPF:1;
193 uint32_t STOPF:1;
194 uint32_t:3;
195 uint32_t WKRLLOVRF:1;
196 uint32_t WKAPIF:1;
197 uint32_t WKRTCF:1;
198 uint32_t PWKSCRF:8;
199 uint32_t SLEEP:1;
200 uint32_t STOP:1;
201 uint32_t:1;
202 uint32_t PKREL:1;
203 uint32_t SLP12EN:1;
204 uint32_t RAMSEL:3;
205 uint32_t PWKSRIE:8;
206 } B;
207 } PSCR; /* Power Status and Control Register */
208
209 uint32_t crp_reserved5[3];
210
211 union {
212 uint32_t R;
213 struct {
214 uint32_t LVI5IE:1;
215 uint32_t LVI5HIE:1;
216 uint32_t LVI5F:1;
217 uint32_t LVI5HF:1;
218 uint32_t LVI5LOCK:1;
219 uint32_t LVI5RE:1;
220 uint32_t:9;
221 uint32_t BYPDIS:1;
222 uint32_t:16;
223 } B;
224 } SOCSC; /* LVI Status and Control Register */
225
226 };
227/****************************************************************************/
228/* MODULE : DMAMUX */
229/****************************************************************************/
230 struct DMAMUX_tag {
231 union {
232 uint8_t R;
233 struct {
234 uint8_t ENBL:1;
235 uint8_t TRIG:1;
236 uint8_t SOURCE:6;
237 } B;
238 } CHCONFIG[16]; /* DMA Channel Configuration Register */
239
240 };
241/****************************************************************************/
242/* MODULE : DSPI */
243/****************************************************************************/
244 struct DSPI_tag {
245 union DSPI_MCR_tag {
246 uint32_t R;
247 struct {
248 uint32_t MSTR:1;
249 uint32_t CONT_SCKE:1;
250 uint32_t DCONF:2;
251 uint32_t FRZ:1;
252 uint32_t MTFE:1;
253 uint32_t PCSSE:1;
254 uint32_t ROOE:1;
255 uint32_t:2;
256 uint32_t PCSIS5:1;
257 uint32_t PCSIS4:1;
258 uint32_t PCSIS3:1;
259 uint32_t PCSIS2:1;
260 uint32_t PCSIS1:1;
261 uint32_t PCSIS0:1;
262 uint32_t:1;
263 uint32_t MDIS:1;
264 uint32_t DIS_TXF:1;
265 uint32_t DIS_RXF:1;
266 uint32_t CLR_TXF:1;
267 uint32_t CLR_RXF:1;
268 uint32_t SMPL_PT:2;
269 uint32_t:7;
270 uint32_t HALT:1;
271 } B;
272 } MCR; /* Module Configuration Register */
273
274 uint32_t dspi_reserved1;
275
276 union {
277 uint32_t R;
278 struct {
279 uint32_t SPI_TCNT:16;
280 uint32_t:16;
281 } B;
282 } TCR;
283
284 union DSPI_CTAR_tag {
285 uint32_t R;
286 struct {
287 uint32_t DBR:1;
288 uint32_t FMSZ:4;
289 uint32_t CPOL:1;
290 uint32_t CPHA:1;
291 uint32_t LSBFE:1;
292 uint32_t PCSSCK:2;
293 uint32_t PASC:2;
294 uint32_t PDT:2;
295 uint32_t PBR:2;
296 uint32_t CSSCK:4;
297 uint32_t ASC:4;
298 uint32_t DT:4;
299 uint32_t BR:4;
300 } B;
301 } CTAR[8]; /* Clock and Transfer Attributes Registers */
302
303 union DSPI_SR_tag {
304 uint32_t R;
305 struct {
306 uint32_t TCF:1;
307 uint32_t TXRXS:1;
308 uint32_t:1;
309 uint32_t EOQF:1;
310 uint32_t TFUF:1;
311 uint32_t:1;
312 uint32_t TFFF:1;
313 uint32_t:5;
314 uint32_t RFOF:1;
315 uint32_t:1;
316 uint32_t RFDF:1;
317 uint32_t:1;
318 uint32_t TXCTR:4;
319 uint32_t TXNXTPTR:4;
320 uint32_t RXCTR:4;
321 uint32_t POPNXTPTR:4;
322 } B;
323 } SR; /* Status Register */
324
325 union DSPI_RSER_tag {
326 uint32_t R;
327 struct {
328 uint32_t TCF_RE:1;
329 uint32_t:2;
330 uint32_t EOQFRE:1;
331 uint32_t TFUFRE:1;
332 uint32_t:1;
333 uint32_t TFFFRE:1;
334 uint32_t TFFFDIRS:1;
335 uint32_t:4;
336 uint32_t RFOFRE:1;
337 uint32_t:1;
338 uint32_t RFDFRE:1;
339 uint32_t RFDFDIRS:1;
340 uint32_t:16;
341 } B;
342 } RSER; /* DMA/Interrupt Request Select and Enable Register */
343
344 union DSPI_PUSHR_tag {
345 uint32_t R;
346 struct {
347 uint32_t CONT:1;
348 uint32_t CTAS:3;
349 uint32_t EOQ:1;
350 uint32_t CTCNT:1;
351 uint32_t:4;
352 uint32_t PCS5:1;
353 uint32_t PCS4:1;
354 uint32_t PCS3:1;
355 uint32_t PCS2:1;
356 uint32_t PCS1:1;
357 uint32_t PCS0:1;
358 uint32_t TXDATA:16;
359 } B;
360 } PUSHR; /* PUSH TX FIFO Register */
361
362 union DSPI_POPR_tag {
363 uint32_t R;
364 struct {
365 uint32_t:16;
366 uint32_t RXDATA:16;
367 } B;
368 } POPR; /* POP RX FIFO Register */
369
370 union {
371 uint32_t R;
372 struct {
373 uint32_t TXCMD:16;
374 uint32_t TXDATA:16;
375 } B;
376 } TXFR[4]; /* Transmit FIFO Registers */
377
378 uint32_t DSPI_reserved_txf[12];
379
380 union {
381 uint32_t R;
382 struct {
383 uint32_t:16;
384 uint32_t RXDATA:16;
385 } B;
386 } RXFR[4]; /* Transmit FIFO Registers */
387
388 uint32_t DSPI_reserved_rxf[12];
389
390 union {
391 uint32_t R;
392 struct {
393 uint32_t:12;
394 uint32_t TXSS:1;
395 uint32_t:2;
396 uint32_t CID:1;
397 uint32_t DCONT:1;
398 uint32_t DSICTAS:3;
399 uint32_t:6;
400 uint32_t DPCS5:1;
401 uint32_t DPCS4:1;
402 uint32_t DPCS3:1;
403 uint32_t DPCS2:1;
404 uint32_t DPCS1:1;
405 uint32_t DPCS0:1;
406 } B;
407 } DSICR; /* DSI Configuration Register */
408
409 union {
410 uint32_t R;
411 struct {
412 uint32_t:16;
413 uint32_t SER_DATA:16;
414 } B;
415 } SDR; /* DSI Serialization Data Register */
416
417 union {
418 uint32_t R;
419 struct {
420 uint32_t:16;
421 uint32_t ASER_DATA:16;
422 } B;
423 } ASDR; /* DSI Alternate Serialization Data Register */
424
425 union {
426 uint32_t R;
427 struct {
428 uint32_t:16;
429 uint32_t COMP_DATA:16;
430 } B;
431 } COMPR; /* DSI Transmit Comparison Register */
432
433 union {
434 uint32_t R;
435 struct {
436 uint32_t:16;
437 uint32_t DESER_DATA:16;
438 } B;
439 } DDR; /* DSI deserialization Data Register */
440
441 };
442/****************************************************************************/
443/* MODULE : External Bus Interface (EBI) */
444/****************************************************************************/
445
446/* CS_tag instantiated within EBI_tag */
447 struct EBI_CS_tag {
448 union { /* Base Register Bank */
449 uint32_t R;
450 struct {
451 uint32_t BA:17;
452 uint32_t:3;
453 uint32_t PS:1;
454 uint32_t:3;
455 uint32_t AD_MUX:1;
456 uint32_t BL:1;
457 uint32_t WEBS:1;
458 uint32_t TBDIP:1;
459 uint32_t:1;
460 uint32_t SETA:1;
461 uint32_t BI:1;
462 uint32_t V:1;
463 } B;
464 } BR;
465
466 union { /* Option Register Bank */
467 uint32_t R;
468 struct {
469 uint32_t AM:17;
470 uint32_t:7;
471 uint32_t SCY:4;
472 uint32_t:1;
473 uint32_t BSCY:2;
474 uint32_t:1;
475 } B;
476 } OR;
477 };
478
479 struct EBI_CAL_CS_tag {
480 uint32_t ebi_cal_cs_reserved [2];
481 };
482
483 struct EBI_tag {
484 union EBI_MCR_tag { /* Module Configuration Register */
485 uint32_t R;
486 struct {
487 uint32_t:16;
488 uint32_t ACGE:1;
489 uint32_t EXTM:1;
490 uint32_t EARB:1;
491 uint32_t:6;
492 uint32_t MDIS:1;
493 uint32_t:3;
494 uint32_t D16_31:1;
495 uint32_t AD_MUX:1;
496 uint32_t DBM:1;
497 } B;
498 } MCR;
499
500 uint32_t EBI_reserved1;
501
502 union { /* Transfer Error Status Register */
503 uint32_t R;
504 struct {
505 uint32_t:30;
506 uint32_t TEAF:1;
507 uint32_t BMTF:1;
508 } B;
509 } TESR;
510
511 union { /* Bus Monitor Control Register */
512 uint32_t R;
513 struct {
514 uint32_t:16;
515 uint32_t BMT:8;
516 uint32_t BME:1;
517 uint32_t:7;
518 } B;
519 } BMCR;
520
521 /* Roll in 3x CS registers */
522 struct EBI_CS_tag CS[4];
523
524 uint32_t EBI_reserved2[4];
525
526 struct EBI_CAL_CS_tag CAL_CS[4];
527 };
528/****************************************************************************/
529/* MODULE : EMIOS */
530/****************************************************************************/
531 struct EMIOS_tag {
532 union EMIOS_MCR_tag {
533 uint32_t R;
534 struct {
535 uint32_t:1;
536 uint32_t MDIS:1;
537 uint32_t FRZ:1;
538 uint32_t GTBE:1;
539 uint32_t:1;
540 uint32_t GPREN:1;
541 uint32_t:10;
542 uint32_t GPRE:8;
543 uint32_t:8;
544 } B;
545 } MCR; /* Module Configuration Register */
546
547 union {
548 uint32_t R;
549 struct {
550 uint32_t:8;
551 uint32_t F23:1;
552 uint32_t F22:1;
553 uint32_t F21:1;
554 uint32_t F20:1;
555 uint32_t F19:1;
556 uint32_t F18:1;
557 uint32_t F17:1;
558 uint32_t F16:1;
559 uint32_t F15:1;
560 uint32_t F14:1;
561 uint32_t F13:1;
562 uint32_t F12:1;
563 uint32_t F11:1;
564 uint32_t F10:1;
565 uint32_t F9:1;
566 uint32_t F8:1;
567 uint32_t F7:1;
568 uint32_t F6:1;
569 uint32_t F5:1;
570 uint32_t F4:1;
571 uint32_t F3:1;
572 uint32_t F2:1;
573 uint32_t F1:1;
574 uint32_t F0:1;
575 } B;
576 } GFG; /* Global FLAG Register */
577
578 union {
579 uint32_t R;
580 struct {
581 uint32_t:8;
582 uint32_t OU23:1;
583 uint32_t OU22:1;
584 uint32_t OU21:1;
585 uint32_t OU20:1;
586 uint32_t OU19:1;
587 uint32_t OU18:1;
588 uint32_t OU17:1;
589 uint32_t OU16:1;
590 uint32_t OU15:1;
591 uint32_t OU14:1;
592 uint32_t OU13:1;
593 uint32_t OU12:1;
594 uint32_t OU11:1;
595 uint32_t OU10:1;
596 uint32_t OU9:1;
597 uint32_t OU8:1;
598 uint32_t OU7:1;
599 uint32_t OU6:1;
600 uint32_t OU5:1;
601 uint32_t OU4:1;
602 uint32_t OU3:1;
603 uint32_t OU2:1;
604 uint32_t OU1:1;
605 uint32_t OU0:1;
606 } B;
607 } OUDR; /* Output Update Disable Register */
608
609 union {
610 uint32_t R;
611 struct {
612 uint32_t:8;
613 uint32_t UC23:1;
614 uint32_t UC22:1;
615 uint32_t UC21:1;
616 uint32_t UC20:1;
617 uint32_t UC19:1;
618 uint32_t UC18:1;
619 uint32_t UC17:1;
620 uint32_t UC16:1;
621 uint32_t UC15:1;
622 uint32_t UC14:1;
623 uint32_t UC13:1;
624 uint32_t UC12:1;
625 uint32_t UC11:1;
626 uint32_t UC10:1;
627 uint32_t UC9:1;
628 uint32_t UC8:1;
629 uint32_t UC7:1;
630 uint32_t UC6:1;
631 uint32_t UC5:1;
632 uint32_t UC4:1;
633 uint32_t UC3:1;
634 uint32_t UC2:1;
635 uint32_t UC1:1;
636 uint32_t UC0:1;
637 } B;
638 } UCDIS; /* Disable Channel Register */
639
640 uint32_t emios_reserved1[4];
641
642 struct EMIOS_CH_tag {
643 union {
644 uint32_t R;
645 struct {
646 uint32_t:16;
647 uint32_t A:16; /* Channel A Data Register */
648 } B;
649 } CADR;
650
651 union {
652 uint32_t R;
653 struct {
654 uint32_t:16;
655 uint32_t B:16; /* Channel B Data Register */
656 } B;
657 } CBDR;
658
659 union {
660 uint32_t R; /* Channel Counter Register */
661 struct {
662 uint32_t:16;
663 uint32_t C:16; /* Channel C Data Register */
664 } B;
665 } CCNTR;
666
667 union EMIOS_CCR_tag {
668 uint32_t R;
669 struct {
670 uint32_t FREN:1;
671 uint32_t ODIS:1;
672 uint32_t ODISSL:2;
673 uint32_t UCPRE:2;
674 uint32_t UCPREN:1;
675 uint32_t DMA:1;
676 uint32_t:1;
677 uint32_t IF:4;
678 uint32_t FCK:1;
679 uint32_t FEN:1;
680 uint32_t:3;
681 uint32_t FORCMA:1;
682 uint32_t FORCMB:1;
683 uint32_t:1;
684 uint32_t BSL:2;
685 uint32_t EDSEL:1;
686 uint32_t EDPOL:1;
687 uint32_t MODE:7;
688 } B;
689 } CCR; /* Channel Control Register */
690
691 union EMIOS_CSR_tag {
692 uint32_t R;
693 struct {
694 uint32_t OVR:1;
695 uint32_t:15;
696 uint32_t OVFL:1;
697 uint32_t:12;
698 uint32_t UCIN:1;
699 uint32_t UCOUT:1;
700 uint32_t FLAG:1;
701 } B;
702 } CSR; /* Channel Status Register */
703
704 union {
705 uint32_t R; /* Alternate Channel A Data Register */
706 } ALTA;
707
708 uint32_t emios_channel_reserved[2];
709
710 } CH[24];
711
712 };
713/****************************************************************************/
714/* MODULE : EQADC */
715/****************************************************************************/
716 struct EQADC_tag {
717 union {
718 uint32_t R;
719 struct {
720 uint32_t:30;
721 uint32_t DBG:2;
722 } B;
723 } MCR; /* Module Configuration Register */
724
725 uint32_t eqadc_reserved0;
726
727 union {
728 uint32_t R;
729 struct {
730 uint32_t:6;
731 uint32_t NMF:26;
732 } B;
733 } NMSFR; /* Null Message Send Format Register */
734
735 union {
736 uint32_t R;
737 struct {
738 uint32_t:28;
739 uint32_t DFL:4;
740 } B;
741 } ETDFR; /* External Trigger Digital Filter Register */
742
743 union {
744 uint32_t R;
745 struct {
746 uint32_t CF_PUSH:32;
747 } B;
748 } CFPR[6]; /* CFIFO Push Registers */
749
750 uint32_t eqadc_reserved1;
751
752 uint32_t eqadc_reserved2;
753
754 union {
755 uint32_t R;
756 struct {
757 uint32_t:16;
758 uint32_t RF_POP:16;
759 } B;
760 } RFPR[6]; /* Result FIFO Pop Registers */
761
762 uint32_t eqadc_reserved3;
763
764 uint32_t eqadc_reserved4;
765
766 union {
767 uint16_t R;
768 struct {
769 uint16_t:5;
770 uint16_t SSE:1;
771 uint16_t CFINV:1;
772 uint16_t:1;
773 uint16_t MODE:4;
774 uint16_t:4;
775 } B;
776 } CFCR[6]; /* CFIFO Control Registers */
777
778 uint32_t eqadc_reserved5;
779
780 union {
781 uint16_t R;
782 struct {
783 uint16_t NCIE:1;
784 uint16_t TORIE:1;
785 uint16_t PIE:1;
786 uint16_t EOQIE:1;
787 uint16_t CFUIE:1;
788 uint16_t:1;
789 uint16_t CFFE:1;
790 uint16_t CFFS:1;
791 uint16_t:4;
792 uint16_t RFOIE:1;
793 uint16_t:1;
794 uint16_t RFDE:1;
795 uint16_t RFDS:1;
796 } B;
797 } IDCR[6]; /* Interrupt and DMA Control Registers */
798
799 uint32_t eqadc_reserved6;
800
801 union {
802 uint32_t R;
803 struct {
804 uint32_t NCF:1;
805 uint32_t TORF:1;
806 uint32_t PF:1;
807 uint32_t EOQF:1;
808 uint32_t CFUF:1;
809 uint32_t SSS:1;
810 uint32_t CFFF:1;
811 uint32_t:5;
812 uint32_t RFOF:1;
813 uint32_t:1;
814 uint32_t RFDF:1;
815 uint32_t:1;
816 uint32_t CFCTR:4;
817 uint32_t TNXTPTR:4;
818 uint32_t RFCTR:4;
819 uint32_t POPNXTPTR:4;
820 } B;
821 } FISR[6]; /* FIFO and Interrupt Status Registers */
822
823 uint32_t eqadc_reserved7;
824
825 uint32_t eqadc_reserved8;
826
827 union {
828 uint16_t R;
829 struct {
830 uint16_t:5;
831 uint16_t TC_CF:11;
832 } B;
833 } CFTCR[6]; /* CFIFO Transfer Counter Registers */
834
835 uint32_t eqadc_reserved9;
836
837 union {
838 uint32_t R;
839 struct {
840 uint32_t CFS0_T0:2;
841 uint32_t CFS1_T0:2;
842 uint32_t CFS2_T0:2;
843 uint32_t CFS3_T0:2;
844 uint32_t CFS4_T0:2;
845 uint32_t CFS5_T0:2;
846 uint32_t:5;
847 uint32_t LCFT0:4;
848 uint32_t TC_LCFT0:11;
849 } B;
850 } CFSSR0; /* CFIFO Status Register 0 */
851
852 uint32_t eqadc_reserved10[2];
853
854 union {
855 uint32_t R;
856 struct {
857 uint32_t CFS0:2;
858 uint32_t CFS1:2;
859 uint32_t CFS2:2;
860 uint32_t CFS3:2;
861 uint32_t CFS4:2;
862 uint32_t CFS5:2;
863 uint32_t:20;
864 } B;
865 } CFSR;
866
867 uint32_t eqadc_reserved11[20];
868
869 struct {
870 union {
871 uint32_t R;
872 struct {
873 uint32_t:32;
874 } B;
875 } R[4];
876
877 uint32_t eqadc_reserved12[12];
878
879 } CF[6];
880
881 uint32_t eqadc_reserved13[32];
882
883 struct {
884 union {
885 uint32_t R;
886 struct {
887 uint32_t:32;
888 } B;
889 } R[4];
890
891 uint32_t eqadc_reserved14[12];
892
893 } RF[6];
894
895 };
896/****************************************************************************/
897/* MODULE : eSCI */
898/****************************************************************************/
899 struct ESCI_tag {
900 union ESCI_CR1_tag {
901 uint32_t R;
902 struct {
903 uint32_t:3;
904 uint32_t SBR:13;
905 uint32_t LOOPS:1;
906 uint32_t:1;
907 uint32_t RSRC:1;
908 uint32_t M:1;
909 uint32_t WAKE:1;
910 uint32_t ILT:1;
911 uint32_t PE:1;
912 uint32_t PT:1;
913 uint32_t TIE:1;
914 uint32_t TCIE:1;
915 uint32_t RIE:1;
916 uint32_t ILIE:1;
917 uint32_t TE:1;
918 uint32_t RE:1;
919 uint32_t RWU:1;
920 uint32_t SBK:1;
921 } B;
922 } CR1; /* Control Register 1 */
923
924 union ESCI_CR2_tag {
925 uint16_t R;
926 struct {
927 uint16_t MDIS:1;
928 uint16_t FBR:1;
929 uint16_t BSTP:1;
930 uint16_t IEBERR:1;
931 uint16_t RXDMA:1;
932 uint16_t TXDMA:1;
933 uint16_t BRK13:1;
934 uint16_t TXDIR:1;
935 uint16_t BESM13:1;
936 uint16_t SBSTP:1;
937 uint16_t:1;
938 uint16_t PMSK:1;
939 uint16_t ORIE:1;
940 uint16_t NFIE:1;
941 uint16_t FEIE:1;
942 uint16_t PFIE:1;
943 } B;
944 } CR2; /* Control Register 2 */
945
946 union ESCI_DR_tag {
947 uint16_t R;
948 struct {
949 uint16_t R8:1;
950 uint16_t T8:1;
951 uint16_t:6;
952 uint8_t D;
953 } B;
954 } DR; /* Data Register */
955
956 union ESCI_SR_tag {
957 uint32_t R;
958 struct {
959 uint32_t TDRE:1;
960 uint32_t TC:1;
961 uint32_t RDRF:1;
962 uint32_t IDLE:1;
963 uint32_t OR:1;
964 uint32_t NF:1;
965 uint32_t FE:1;
966 uint32_t PF:1;
967 uint32_t:3;
968 uint32_t BERR:1;
969 uint32_t:3;
970 uint32_t RAF:1;
971 uint32_t RXRDY:1;
972 uint32_t TXRDY:1;
973 uint32_t LWAKE:1;
974 uint32_t STO:1;
975 uint32_t PBERR:1;
976 uint32_t CERR:1;
977 uint32_t CKERR:1;
978 uint32_t FRC:1;
979 uint32_t:6;
980 uint32_t UREQ:1;
981 uint32_t OVFL:1;
982 } B;
983 } SR; /* Status Register */
984
985 union {
986 uint32_t R;
987 struct {
988 uint32_t LRES:1;
989 uint32_t WU:1;
990 uint32_t WUD0:1;
991 uint32_t WUD1:1;
992 uint32_t LDBG:1;
993 uint32_t DSF:1;
994 uint32_t PRTY:1;
995 uint32_t LIN:1;
996 uint32_t RXIE:1;
997 uint32_t TXIE:1;
998 uint32_t WUIE:1;
999 uint32_t STIE:1;
1000 uint32_t PBIE:1;
1001 uint32_t CIE:1;
1002 uint32_t CKIE:1;
1003 uint32_t FCIE:1;
1004 uint32_t:6;
1005 uint32_t UQIE:1;
1006 uint32_t OFIE:1;
1007 uint32_t:8;
1008 } B;
1009 } LCR; /* LIN Control Register */
1010
1011 union {
1012 uint32_t R;
1013 } LTR; /* LIN Transmit Register */
1014
1015 union {
1016 uint32_t R;
1017 } LRR; /* LIN Recieve Register */
1018
1019 union {
1020 uint32_t R;
1021 } LPR; /* LIN CRC Polynom Register */
1022
1023 };
1024/****************************************************************************/
1025/* MODULE : FLASH */
1026/****************************************************************************/
1027 struct FLASH_tag {
1028 union { /* Module Configuration Register */
1029 uint32_t R;
1030 struct {
1031 uint32_t:3;
1032 uint32_t SFS:1;
1033 uint32_t SIZE:4;
1034 uint32_t:1;
1035 uint32_t LAS:3;
1036 uint32_t:3;
1037 uint32_t MAS:1;
1038 uint32_t EER:1;
1039 uint32_t RWE:1;
1040 uint32_t BBEPE:1;
1041 uint32_t EPE:1;
1042 uint32_t PEAS:1;
1043 uint32_t DONE:1;
1044 uint32_t PEG:1;
1045 uint32_t:1;
1046 uint32_t PRD:1;
1047 uint32_t STOP:1;
1048 uint32_t:1;
1049 uint32_t PGM:1;
1050 uint32_t PSUS:1;
1051 uint32_t ERS:1;
1052 uint32_t ESUS:1;
1053 uint32_t EHV:1;
1054 } B;
1055 } MCR;
1056
1057 union LMLR_tag { /* Low/Mid Address Space Block Locking Register */
1058 uint32_t R;
1059 struct {
1060 uint32_t LME:1;
1061 uint32_t:10;
1062 uint32_t SLOCK:1;
1063 uint32_t:2;
1064 uint32_t MLOCK:2;
1065 uint32_t:6;
1066 uint32_t LLOCK:10;
1067 } B;
1068 } LMLR; /* Legacy naming - refer to LML in Reference Manual */
1069
1070 union HLR_tag { /* High Address Space Block Locking Register */
1071 uint32_t R;
1072 struct {
1073 uint32_t HBE:1;
1074 uint32_t:23;
1075 uint32_t HBLOCK:8;
1076 } B;
1077 } HLR; /* Legacy naming - refer to HBL in Reference Manual */
1078
1079 union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */
1080 uint32_t R;
1081 struct {
1082 uint32_t SLE:1;
1083 uint32_t:10;
1084 uint32_t SSLOCK:1;
1085 uint32_t:2;
1086 uint32_t SMLOCK:2;
1087 uint32_t:6;
1088 uint32_t SLLOCK:10;
1089 } B;
1090 } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */
1091
1092 union { /* Low/Mid Address Space Block Select Register */
1093 uint32_t R;
1094 struct {
1095 uint32_t:14;
1096 uint32_t MSEL:2;
1097 uint32_t:6;
1098 uint32_t LSEL:10;
1099 } B;
1100 } LMSR; /* Legacy naming - refer to LMS in Reference Manual */
1101
1102 union { /* High Address Space Block Select Register */
1103 uint32_t R;
1104 struct {
1105 uint32_t:28;
1106 uint32_t HBSEL:4;
1107 } B;
1108 } HSR; /* Legacy naming - refer to HBS in Reference Manual */
1109
1110 union { /* Address Register */
1111 uint32_t R;
1112 struct {
1113 uint32_t:10;
1114 uint32_t ADDR:19;
1115 uint32_t:3;
1116 } B;
1117 } AR; /* Legacy naming - refer to ADR in Reference Manual */
1118
1119 union { /* Platform Flash Configuration Register for Port 0 */
1120 uint32_t R;
1121 struct {
1122 uint32_t LBCFG:4;
1123 uint32_t ARB:1;
1124 uint32_t PRI:1;
1125 uint32_t:5;
1126 uint32_t M4PFE:1;
1127 uint32_t M3PFE:1;
1128 uint32_t M2PFE:1;
1129 uint32_t M1PFE:1;
1130 uint32_t M0PFE:1;
1131 uint32_t APC:3;
1132 uint32_t WWSC:2;
1133 uint32_t RWSC:3;
1134 uint32_t:1;
1135 uint32_t DPFEN:1;
1136 uint32_t:1;
1137 uint32_t IPFEN:1;
1138 uint32_t:1;
1139 uint32_t PFLIM:2;
1140 uint32_t BFEN:1;
1141 } B;
1142 } PFCRP0;
1143
1144 union { /* Platform Flash Configuration Register for Port 1 */
1145 uint32_t R;
1146 struct {
1147 uint32_t LBCFG:4;
1148 uint32_t:7;
1149 uint32_t M4PFE:1;
1150 uint32_t M3PFE:1;
1151 uint32_t M2PFE:1;
1152 uint32_t M1PFE:1;
1153 uint32_t M0PFE:1;
1154 uint32_t APC:3;
1155 uint32_t WWSC:2;
1156 uint32_t RWSC:3;
1157 uint32_t:1;
1158 uint32_t DPFEN:1;
1159 uint32_t:1;
1160 uint32_t IPFEN:1;
1161 uint32_t:1;
1162 uint32_t PFLIM:2;
1163 uint32_t BFEN:1;
1164 } B;
1165 } PFCRP1;
1166
1167 };
1168/****************************************************************************/
1169/* MODULE : FlexCAN */
1170/****************************************************************************/
1171 struct FLEXCAN_tag {
1172 union {
1173 uint32_t R;
1174 struct {
1175 uint32_t MDIS:1;
1176 uint32_t FRZ:1;
1177 uint32_t FEN:1;
1178 uint32_t HALT:1;
1179 uint32_t NOTRDY:1;
1180 uint32_t WAKMSK:1;
1181 uint32_t SOFTRST:1;
1182 uint32_t FRZACK:1;
1183 uint32_t SUPV:1;
1184 uint32_t SLFWAK:1;
1185 uint32_t WRNEN:1;
1186 uint32_t LPMACK:1;
1187 uint32_t WAKSRC:1;
1188 uint32_t DOZE:1;
1189 uint32_t SRXDIS:1;
1190 uint32_t BCC:1;
1191 uint32_t:2;
1192 uint32_t LPRIO_EN:1;
1193 uint32_t AEN:1;
1194 uint32_t:2;
1195 uint32_t IDAM:2;
1196 uint32_t:2;
1197 uint32_t MAXMB:6;
1198 } B;
1199 } MCR; /* Module Configuration Register */
1200
1201 union {
1202 uint32_t R;
1203 struct {
1204 uint32_t PRESDIV:8;
1205 uint32_t RJW:2;
1206 uint32_t PSEG1:3;
1207 uint32_t PSEG2:3;
1208 uint32_t BOFFMSK:1;
1209 uint32_t ERRMSK:1;
1210 uint32_t CLKSRC:1;
1211 uint32_t LPB:1;
1212 uint32_t TWRNMSK:1;
1213 uint32_t RWRNMSK:1;
1214 uint32_t:2;
1215 uint32_t SMP:1;
1216 uint32_t BOFFREC:1;
1217 uint32_t TSYN:1;
1218 uint32_t LBUF:1;
1219 uint32_t LOM:1;
1220 uint32_t PROPSEG:3;
1221 } B;
1222 } CTRL; /* Control Register */
1223
1224 union {
1225 uint32_t R;
1226 } TIMER; /* Free Running Timer */
1227
1228 uint32_t FLEXCAN_reserved1;
1229
1230 union {
1231 uint32_t R;
1232 struct {
1233 uint32_t MI:32;
1234 } B;
1235 } RXGMASK; /* RX Global Mask */
1236
1237 union {
1238 uint32_t R;
1239 struct {
1240 uint32_t MI:32;
1241 } B;
1242 } RX14MASK; /* RX 14 Mask */
1243
1244 union {
1245 uint32_t R;
1246 struct {
1247 uint32_t MI:32;
1248 } B;
1249 } RX15MASK; /* RX 15 Mask */
1250
1251 union {
1252 uint32_t R;
1253 struct {
1254 uint32_t:16;
1255 uint32_t RXECNT:8;
1256 uint32_t TXECNT:8;
1257 } B;
1258 } ECR; /* Error Counter Register */
1259
1260 union {
1261 uint32_t R;
1262 struct {
1263 uint32_t:14;
1264 uint32_t TWRNINT:1;
1265 uint32_t RWRNINT:1;
1266 uint32_t BIT1ERR:1;
1267 uint32_t BIT0ERR:1;
1268 uint32_t ACKERR:1;
1269 uint32_t CRCERR:1;
1270 uint32_t FRMERR:1;
1271 uint32_t STFERR:1;
1272 uint32_t TXWRN:1;
1273 uint32_t RXWRN:1;
1274 uint32_t IDLE:1;
1275 uint32_t TXRX:1;
1276 uint32_t FLTCONF:2;
1277 uint32_t:1;
1278 uint32_t BOFFINT:1;
1279 uint32_t ERRINT:1;
1280 uint32_t WAKINT:1;
1281 } B;
1282 } ESR; /* Error and Status Register */
1283
1284 union {
1285 uint32_t R;
1286 struct {
1287 uint32_t BUF63M:1;
1288 uint32_t BUF62M:1;
1289 uint32_t BUF61M:1;
1290 uint32_t BUF60M:1;
1291 uint32_t BUF59M:1;
1292 uint32_t BUF58M:1;
1293 uint32_t BUF57M:1;
1294 uint32_t BUF56M:1;
1295 uint32_t BUF55M:1;
1296 uint32_t BUF54M:1;
1297 uint32_t BUF53M:1;
1298 uint32_t BUF52M:1;
1299 uint32_t BUF51M:1;
1300 uint32_t BUF50M:1;
1301 uint32_t BUF49M:1;
1302 uint32_t BUF48M:1;
1303 uint32_t BUF47M:1;
1304 uint32_t BUF46M:1;
1305 uint32_t BUF45M:1;
1306 uint32_t BUF44M:1;
1307 uint32_t BUF43M:1;
1308 uint32_t BUF42M:1;
1309 uint32_t BUF41M:1;
1310 uint32_t BUF40M:1;
1311 uint32_t BUF39M:1;
1312 uint32_t BUF38M:1;
1313 uint32_t BUF37M:1;
1314 uint32_t BUF36M:1;
1315 uint32_t BUF35M:1;
1316 uint32_t BUF34M:1;
1317 uint32_t BUF33M:1;
1318 uint32_t BUF32M:1;
1319 } B;
1320 } IMASK2; /* Interruput Masks Register */
1321
1322 union {
1323 uint32_t R;
1324 struct {
1325 uint32_t BUF31M:1;
1326 uint32_t BUF30M:1;
1327 uint32_t BUF29M:1;
1328 uint32_t BUF28M:1;
1329 uint32_t BUF27M:1;
1330 uint32_t BUF26M:1;
1331 uint32_t BUF25M:1;
1332 uint32_t BUF24M:1;
1333 uint32_t BUF23M:1;
1334 uint32_t BUF22M:1;
1335 uint32_t BUF21M:1;
1336 uint32_t BUF20M:1;
1337 uint32_t BUF19M:1;
1338 uint32_t BUF18M:1;
1339 uint32_t BUF17M:1;
1340 uint32_t BUF16M:1;
1341 uint32_t BUF15M:1;
1342 uint32_t BUF14M:1;
1343 uint32_t BUF13M:1;
1344 uint32_t BUF12M:1;
1345 uint32_t BUF11M:1;
1346 uint32_t BUF10M:1;
1347 uint32_t BUF09M:1;
1348 uint32_t BUF08M:1;
1349 uint32_t BUF07M:1;
1350 uint32_t BUF06M:1;
1351 uint32_t BUF05M:1;
1352 uint32_t BUF04M:1;
1353 uint32_t BUF03M:1;
1354 uint32_t BUF02M:1;
1355 uint32_t BUF01M:1;
1356 uint32_t BUF00M:1;
1357 } B;
1358 } IMASK1; /* Interruput Masks Register */
1359
1360 union {
1361 uint32_t R;
1362 struct {
1363 uint32_t BUF63I:1;
1364 uint32_t BUF62I:1;
1365 uint32_t BUF61I:1;
1366 uint32_t BUF60I:1;
1367 uint32_t BUF59I:1;
1368 uint32_t BUF58I:1;
1369 uint32_t BUF57I:1;
1370 uint32_t BUF56I:1;
1371 uint32_t BUF55I:1;
1372 uint32_t BUF54I:1;
1373 uint32_t BUF53I:1;
1374 uint32_t BUF52I:1;
1375 uint32_t BUF51I:1;
1376 uint32_t BUF50I:1;
1377 uint32_t BUF49I:1;
1378 uint32_t BUF48I:1;
1379 uint32_t BUF47I:1;
1380 uint32_t BUF46I:1;
1381 uint32_t BUF45I:1;
1382 uint32_t BUF44I:1;
1383 uint32_t BUF43I:1;
1384 uint32_t BUF42I:1;
1385 uint32_t BUF41I:1;
1386 uint32_t BUF40I:1;
1387 uint32_t BUF39I:1;
1388 uint32_t BUF38I:1;
1389 uint32_t BUF37I:1;
1390 uint32_t BUF36I:1;
1391 uint32_t BUF35I:1;
1392 uint32_t BUF34I:1;
1393 uint32_t BUF33I:1;
1394 uint32_t BUF32I:1;
1395 } B;
1396 } IFLAG2; /* Interruput Flag Register */
1397
1398 union {
1399 uint32_t R;
1400 struct {
1401 uint32_t BUF31I:1;
1402 uint32_t BUF30I:1;
1403 uint32_t BUF29I:1;
1404 uint32_t BUF28I:1;
1405 uint32_t BUF27I:1;
1406 uint32_t BUF26I:1;
1407 uint32_t BUF25I:1;
1408 uint32_t BUF24I:1;
1409 uint32_t BUF23I:1;
1410 uint32_t BUF22I:1;
1411 uint32_t BUF21I:1;
1412 uint32_t BUF20I:1;
1413 uint32_t BUF19I:1;
1414 uint32_t BUF18I:1;
1415 uint32_t BUF17I:1;
1416 uint32_t BUF16I:1;
1417 uint32_t BUF15I:1;
1418 uint32_t BUF14I:1;
1419 uint32_t BUF13I:1;
1420 uint32_t BUF12I:1;
1421 uint32_t BUF11I:1;
1422 uint32_t BUF10I:1;
1423 uint32_t BUF09I:1;
1424 uint32_t BUF08I:1;
1425 uint32_t BUF07I:1;
1426 uint32_t BUF06I:1;
1427 uint32_t BUF05I:1;
1428 uint32_t BUF04I:1;
1429 uint32_t BUF03I:1;
1430 uint32_t BUF02I:1;
1431 uint32_t BUF01I:1;
1432 uint32_t BUF00I:1;
1433 } B;
1434 } IFLAG1; /* Interruput Flag Register */
1435
1436 uint32_t FLEXCAN_reserved2[19];
1437
1438 struct canbuf_t {
1439 union {
1440 uint32_t R;
1441 struct {
1442 uint32_t:4;
1443 uint32_t CODE:4;
1444 uint32_t:1;
1445 uint32_t SRR:1;
1446 uint32_t IDE:1;
1447 uint32_t RTR:1;
1448 uint32_t LENGTH:4;
1449 uint32_t TIMESTAMP:16;
1450 } B;
1451 } CS;
1452
1453 union {
1454 uint32_t R;
1455 struct {
1456 uint32_t PRIO:3;
1457 uint32_t STD_ID:11;
1458 uint32_t EXT_ID:18;
1459 } B;
1460 } ID;
1461
1462 union {
1463 uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
1464 uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
1465 uint32_t W[2]; /* Data buffer in words (32 bits) */
1466 uint32_t R[2]; /* Data buffer in words (32 bits) */
1467 } DATA;
1468
1469 } BUF[64];
1470
1471 uint32_t FLEXCAN_reserved3[256];
1472
1473 union {
1474 uint32_t R;
1475 struct {
1476 uint32_t MI:32;
1477 } B;
1478 } RXIMR[64]; /* RX Individual Mask Registers */
1479
1480 };
1481/****************************************************************************/
1482/* MODULE : FMPLL */
1483/****************************************************************************/
1484 struct FMPLL_tag {
1485
1486 uint32_t FMPLL_reserved0;
1487
1488 union FMPLL_SYNSR_tag { /* Synthesiser Status Register */
1489 uint32_t R;
1490 struct {
1491 uint32_t:22;
1492 uint32_t LOLF:1;
1493 uint32_t LOC:1;
1494 uint32_t MODE:1;
1495 uint32_t PLLSEL:1;
1496 uint32_t PLLREF:1;
1497 uint32_t LOCKS:1;
1498 uint32_t LOCK:1;
1499 uint32_t LOCF:1;
1500 uint32_t CALDONE:1;
1501 uint32_t CALPASS:1;
1502 } B;
1503 } SYNSR;
1504
1505 union FMPLL_ESYNCR1_tag {
1506 uint32_t R;
1507 struct {
1508 uint32_t:1;
1509 uint32_t CLKCFG:3;
1510 uint32_t:8;
1511 uint32_t EPREDIV:4;
1512 uint32_t:8;
1513 uint32_t EMFD:8;
1514 } B;
1515 } ESYNCR1;
1516
1517 union FMPLL_ESYNCR2_tag {
1518 uint32_t R;
1519 struct {
1520 uint32_t:8;
1521 uint32_t LOCEN:1;
1522 uint32_t LOLRE:1;
1523 uint32_t LOCRE:1;
1524 uint32_t LOLIRQ:1;
1525 uint32_t LOCIRQ:1;
1526 uint32_t:1;
1527 uint32_t ERATE:2;
1528 uint32_t:5;
1529 uint32_t EDEPTH:3;
1530 uint32_t:2;
1531 uint32_t ERFD:6;
1532 } B;
1533 } ESYNCR2;
1534
1535 };
1536/****************************************************************************/
1537/* MODULE : i2c */
1538/****************************************************************************/
1539 struct I2C_tag {
1540 union {
1541 uint8_t R;
1542 struct {
1543 uint8_t AD:7;
1544 uint8_t:1;
1545 } B;
1546 } IBAD; /* Module Bus Address Register */
1547
1548 union {
1549 uint8_t R;
1550 struct {
1551 uint8_t MULT:2;
1552 uint8_t ICR:6;
1553 } B;
1554 } IBFD; /* Module Bus Frequency Register */
1555
1556 union {
1557 uint8_t R;
1558 struct {
1559 uint8_t MDIS:1;
1560 uint8_t IBIE:1;
1561 uint8_t MS:1;
1562 uint8_t TX:1;
1563 uint8_t NOACK:1;
1564 uint8_t RSTA:1;
1565 uint8_t DMAEN:1;
1566 uint8_t:1;
1567 } B;
1568 } IBCR; /* Module Bus Control Register */
1569
1570 union {
1571 uint8_t R;
1572 struct {
1573 uint8_t TCF:1;
1574 uint8_t IAAS:1;
1575 uint8_t IBB:1;
1576 uint8_t IBAL:1;
1577 uint8_t:1;
1578 uint8_t SRW:1;
1579 uint8_t IBIF:1;
1580 uint8_t RXAK:1;
1581 } B;
1582 } IBSR; /* Module Status Register */
1583
1584 union {
1585 uint8_t R;
1586 struct {
1587 uint8_t DATA:8;
1588 } B;
1589 } IBDR; /* Module Data Register */
1590
1591 union {
1592 uint8_t R;
1593 struct {
1594 uint8_t BIIE:1;
1595 uint8_t:7;
1596 } B;
1597 } IBIC; /* Module Interrupt Configuration Register */
1598
1599 };
1600/****************************************************************************/
1601/* MODULE : INTC */
1602/****************************************************************************/
1603 struct INTC_tag {
1604 union {
1605 uint32_t R;
1606 struct {
1607 uint32_t:18;
1608 uint32_t VTES_PRC1:1;
1609 uint32_t:4;
1610 uint32_t HVEN_PRC1:1;
1611 uint32_t:2;
1612 uint32_t VTES:1;
1613 uint32_t:4;
1614 uint32_t HVEN:1;
1615 } B;
1616 } MCR; /* Module Configuration Register */
1617
1618 int32_t INTC_reserved1;
1619
1620 union {
1621 uint32_t R;
1622 struct {
1623 uint32_t:28;
1624 uint32_t PRI:4;
1625 } B;
1626 } CPR; /* Processor 0 Current Priority Register */
1627
1628 union {
1629 uint32_t R;
1630 struct {
1631 uint32_t:28;
1632 uint32_t PRI:4;
1633 } B;
1634 } CPR_PRC1; /* Processor 1 Current Priority Register */
1635
1636 union {
1637 uint32_t R;
1638 struct {
1639 uint32_t VTBA:21;
1640 uint32_t INTVEC:9;
1641 uint32_t:2;
1642 } B;
1643 } IACKR; /* Processor 0 Interrupt Acknowledge Register */
1644
1645 union {
1646 uint32_t R;
1647 struct {
1648 uint32_t VTBA_PRC1:21;
1649 uint32_t INTVEC_PRC1:9;
1650 uint32_t:2;
1651 } B;
1652 } IACKR_PRC1; /* Processor 1 Interrupt Acknowledge Register */
1653
1654 union {
1655 uint32_t R;
1656 struct {
1657 uint32_t:32;
1658 } B;
1659 } EOIR; /* Processor 0 End of Interrupt Register */
1660
1661 union {
1662 uint32_t R;
1663 struct {
1664 uint32_t:32;
1665 } B;
1666 } EOIR_PRC1; /* Processor 1 End of Interrupt Register */
1667
1668 union {
1669 uint8_t R;
1670 struct {
1671 uint8_t:6;
1672 uint8_t SET:1;
1673 uint8_t CLR:1;
1674 } B;
1675 } SSCIR[8]; /* Software Set/Clear Interruput Register */
1676
1677 uint32_t intc_reserved2[6];
1678
1679 union {
1680 uint8_t R;
1681 struct {
1682 uint8_t PRC_SEL:2;
1683 uint8_t:2;
1684 uint8_t PRI:4;
1685 } B;
1686 } PSR[294]; /* Software Set/Clear Interrupt Register */
1687
1688 };
1689/****************************************************************************/
1690/* MODULE : MCM */
1691/****************************************************************************/
1692 struct MCM_tag {
1693
1694 uint32_t mcm_reserved1[5];
1695
1696 uint16_t mcm_reserved2;
1697
1698 union {
1699 uint16_t R;
1700 struct {
1701 uint16_t RO:1;
1702 uint16_t:6;
1703 uint16_t SWRWH:1;
1704 uint16_t SWE:1;
1705 uint16_t SWRI:2;
1706 uint16_t SWT:5;
1707 } B;
1708 } SWTCR; /* Software Watchdog Timer Control */
1709
1710 uint8_t mcm_reserved3[3];
1711
1712 union {
1713 uint8_t R;
1714 } SWTSR; /* SWT Service Register */
1715
1716 uint8_t mcm_reserved4[3];
1717
1718 union {
1719 uint8_t R;
1720 struct {
1721 uint8_t:7;
1722 uint8_t SWTIC:1;
1723 } B;
1724 } SWTIR; /* SWT Interrupt Register */
1725
1726 uint32_t mcm_reserved5[1];
1727
1728 union {
1729 uint32_t R;
1730 struct {
1731 uint32_t PRI:1;
1732 uint32_t:31;
1733 } B;
1734 } MUDCR; /* Misc. User Defined Control Register */
1735
1736 uint32_t mcm_reserved6[6];
1737 uint8_t mcm_reserved7[3];
1738
1739 union {
1740 uint8_t R;
1741 struct {
1742 uint8_t:6;
1743 uint8_t ERNCR:1;
1744 uint8_t EFNCR:1;
1745 } B;
1746 } ECR; /* ECC Configuration Register */
1747
1748 uint8_t mcm_reserved8[3];
1749
1750 union {
1751 uint8_t R;
1752 struct {
1753 uint8_t:6;
1754 uint8_t RNCE:1;
1755 uint8_t FNCE:1;
1756 } B;
1757 } ESR; /* ECC Status Register */
1758
1759 uint16_t mcm_reserved9;
1760
1761 union {
1762 uint16_t R;
1763 struct {
1764 uint16_t:6;
1765 uint16_t FRCNCI:1;
1766 uint16_t FR1NCI:1;
1767 uint16_t:1;
1768 uint16_t ERRBIT:7;
1769 } B;
1770 } EEGR; /* ECC Error Generation Register */
1771
1772 uint32_t mcm_reserved10;
1773
1774 union {
1775 uint32_t R;
1776 } FEAR; /* Flash ECC Address Register */
1777
1778 uint16_t mcm_reserved11;
1779
1780 union {
1781 uint8_t R;
1782 struct {
1783 uint8_t:4;
1784 uint8_t FEMR:4;
1785 } B;
1786 } FEMR; /* Flash ECC Master Register */
1787
1788 union {
1789 uint8_t R;
1790 struct {
1791 uint8_t WRITE:1;
1792 uint8_t SIZE:3;
1793 uint8_t PROTECTION:4;
1794 } B;
1795 } FEAT; /* Flash ECC Attributes Register */
1796
1797 union {
1798 uint32_t R;
1799 } FEDRH; /* Flash ECC Data High Register */
1800
1801 union {
1802 uint32_t R;
1803 } FEDRL; /* Flash ECC Data Low Register */
1804
1805 union {
1806 uint32_t R;
1807 struct {
1808 uint32_t REAR:32;
1809 } B;
1810 } REAR; /* RAM ECC Address */
1811
1812 uint16_t mcm_reserved12;
1813
1814 union {
1815 uint8_t R;
1816 struct {
1817 uint8_t:4;
1818 uint8_t REMR:4;
1819 } B;
1820 } REMR; /* RAM ECC Master */
1821
1822 union {
1823 uint8_t R;
1824 struct {
1825 uint8_t WRITE:1;
1826 uint8_t SIZE:3;
1827 uint8_t PROTECTION:4;
1828 } B;
1829 } REAT; /* RAM ECC Attributes Register */
1830
1831 union {
1832 uint32_t R;
1833 } REDRH; /* RAM ECC Data High Register */
1834
1835 union {
1836 uint32_t R;
1837 } REDRL; /* RAMECC Data Low Register */
1838
1839 };
1840/****************************************************************************/
1841/* MODULE : MPU */
1842/****************************************************************************/
1843 struct MPU_tag {
1844 union {
1845 uint32_t R;
1846 struct {
1847 uint32_t SPERR:8;
1848 uint32_t:4;
1849 uint32_t HRL:4;
1850 uint32_t NSP:4;
1851 uint32_t NGRD:4;
1852 uint32_t:7;
1853 uint32_t VLD:1;
1854 } B;
1855 } CESR; /* Module Control/Error Status Register */
1856
1857 uint32_t mpu_reserved1[3];
1858
1859 union {
1860 uint32_t R;
1861 struct {
1862 uint32_t EADDR:32;
1863 } B;
1864 } EAR0;
1865
1866 union {
1867 uint32_t R;
1868 struct {
1869 uint32_t EACD:16;
1870 uint32_t EPID:8;
1871 uint32_t EMN:4;
1872 uint32_t EATTR:3;
1873 uint32_t ERW:1;
1874 } B;
1875 } EDR0;
1876
1877 union {
1878 uint32_t R;
1879 struct {
1880 uint32_t EADDR:32;
1881 } B;
1882 } EAR1;
1883
1884 union {
1885 uint32_t R;
1886 struct {
1887 uint32_t EACD:16;
1888 uint32_t EPID:8;
1889 uint32_t EMN:4;
1890 uint32_t EATTR:3;
1891 uint32_t ERW:1;
1892 } B;
1893 } EDR1;
1894
1895 union {
1896 uint32_t R;
1897 struct {
1898 uint32_t EADDR:32;
1899 } B;
1900 } EAR2;
1901
1902 union {
1903 uint32_t R;
1904 struct {
1905 uint32_t EACD:16;
1906 uint32_t EPID:8;
1907 uint32_t EMN:4;
1908 uint32_t EATTR:3;
1909 uint32_t ERW:1;
1910 } B;
1911 } EDR2;
1912
1913 uint32_t mpu_reserved2[246];
1914
1915 struct {
1916 union {
1917 uint32_t R;
1918 struct {
1919 uint32_t SRTADDR:27;
1920 uint32_t:5;
1921 } B;
1922 } WORD0; /* Region Descriptor n Word 0 */
1923
1924 union {
1925 uint32_t R;
1926 struct {
1927 uint32_t ENDADDR:27;
1928 uint32_t:5;
1929 } B;
1930 } WORD1; /* Region Descriptor n Word 1 */
1931
1932 union {
1933 uint32_t R;
1934 struct {
1935 uint32_t:6;
1936 uint32_t M4RE0:1;
1937 uint32_t M4WE:1;
1938 uint32_t M3PE:1;
1939 uint32_t M3SM:2;
1940 uint32_t M3UM:3;
1941 uint32_t M2PE:1;
1942 uint32_t M2SM:2;
1943 uint32_t M2UM:3;
1944 uint32_t M1PE:1;
1945 uint32_t M1SM:2;
1946 uint32_t M1UM:3;
1947 uint32_t M0PE:1;
1948 uint32_t M0SM:2;
1949 uint32_t M0UM:3;
1950 } B;
1951 } WORD2; /* Region Descriptor n Word 2 */
1952
1953 union {
1954 uint32_t R;
1955 struct {
1956 uint32_t PID:8;
1957 uint32_t PIDMASK:8;
1958 uint32_t:15;
1959 uint32_t VLD:1;
1960 } B;
1961 } WORD3; /* Region Descriptor n Word 3 */
1962
1963 } RGD[16];
1964
1965 uint32_t mpu_reserved3[192];
1966
1967 union {
1968 uint32_t R;
1969 struct {
1970 uint32_t:6;
1971 uint32_t M4RE:1;
1972 uint32_t M4WE:1;
1973 uint32_t M3PE:1;
1974 uint32_t M3SM:2;
1975 uint32_t M3UM:3;
1976 uint32_t M2PE:1;
1977 uint32_t M2SM:2;
1978 uint32_t M2UM:3;
1979 uint32_t M1PE:1;
1980 uint32_t M1SM:2;
1981 uint32_t M1UM:3;
1982 uint32_t M0PE:1;
1983 uint32_t M0SM:2;
1984 uint32_t M0UM:3;
1985 } B;
1986 } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
1987 };
1988/****************************************************************************/
1989/* MODULE : pit */
1990/****************************************************************************/
1991 struct PIT_tag {
1992 union {
1993 uint32_t R;
1994 struct {
1995 uint32_t TSV:32;
1996 } B;
1997 } TLVAL[9];
1998
1999 uint32_t pit_reserved1[23];
2000
2001 union {
2002 uint32_t R;
2003 struct {
2004 uint32_t TVL:32;
2005 } B;
2006 } TVAL[9];
2007
2008 uint32_t pit_reserved2[23];
2009
2010 union {
2011 uint32_t R;
2012 struct {
2013 uint32_t:23;
2014 uint32_t TIF8:1;
2015 uint32_t TIF7:1;
2016 uint32_t TIF6:1;
2017 uint32_t TIF5:1;
2018 uint32_t TIF4:1;
2019 uint32_t TIF3:1;
2020 uint32_t TIF2:1;
2021 uint32_t TIF1:1;
2022 uint32_t RTIF:1;
2023 } B;
2024 } PITFLG;
2025
2026 union {
2027 uint32_t R;
2028 struct {
2029 uint32_t:23;
2030 uint32_t TIE8:1;
2031 uint32_t TIE7:1;
2032 uint32_t TIE6:1;
2033 uint32_t TIE5:1;
2034 uint32_t TIE4:1;
2035 uint32_t TIE3:1;
2036 uint32_t TIE2:1;
2037 uint32_t TIE1:1;
2038 uint32_t RTIE:1;
2039 } B;
2040 } PITINTEN;
2041
2042 union {
2043 uint32_t R;
2044 struct {
2045 uint32_t:23;
2046 uint32_t ISEL8:1;
2047 uint32_t ISEL7:1;
2048 uint32_t ISEL6:1;
2049 uint32_t ISEL5:1;
2050 uint32_t ISEL4:1;
2051 uint32_t ISEL3:1;
2052 uint32_t ISEL2:1;
2053 uint32_t ISEL1:1;
2054 uint32_t:1;
2055 } B;
2056 } PITINTSEL;
2057
2058 union {
2059 uint32_t R;
2060 struct {
2061 uint32_t:23;
2062 uint32_t PEN8:1;
2063 uint32_t PEN7:1;
2064 uint32_t PEN6:1;
2065 uint32_t PEN5:1;
2066 uint32_t PEN4:1;
2067 uint32_t PEN3:1;
2068 uint32_t PEN2:1;
2069 uint32_t PEN1:1;
2070 uint32_t PEN0:1;
2071 } B;
2072 } PITEN;
2073
2074 union {
2075 uint32_t R;
2076 struct {
2077 uint32_t:7;
2078 uint32_t MDIS:1;
2079 uint32_t:24;
2080 } B;
2081 } PITCTRL;
2082
2083 };
2084/****************************************************************************/
2085/* MODULE : sem4 */
2086/****************************************************************************/
2087 struct SEMA4_tag {
2088 union {
2089 uint8_t R;
2090 struct {
2091 uint8_t:6;
2092 uint8_t GTFSM:2;
2093 } B;
2094 } GATE[16]; /* Gate n Register */
2095
2096 uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */
2097
2098 union {
2099 uint16_t R;
2100 struct {
2101 uint16_t INE0:1;
2102 uint16_t INE1:1;
2103 uint16_t INE2:1;
2104 uint16_t INE3:1;
2105 uint16_t INE4:1;
2106 uint16_t INE5:1;
2107 uint16_t INE6:1;
2108 uint16_t INE7:1;
2109 uint16_t INE8:1;
2110 uint16_t INE9:1;
2111 uint16_t INE10:1;
2112 uint16_t INE11:1;
2113 uint16_t INE12:1;
2114 uint16_t INE13:1;
2115 uint16_t INE14:1;
2116 uint16_t INE15:1;
2117 } B;
2118 } CP0INE;
2119
2120 uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */
2121
2122 union {
2123 uint16_t R;
2124 struct {
2125 uint16_t INE0:1;
2126 uint16_t INE1:1;
2127 uint16_t INE2:1;
2128 uint16_t INE3:1;
2129 uint16_t INE4:1;
2130 uint16_t INE5:1;
2131 uint16_t INE6:1;
2132 uint16_t INE7:1;
2133 uint16_t INE8:1;
2134 uint16_t INE9:1;
2135 uint16_t INE10:1;
2136 uint16_t INE11:1;
2137 uint16_t INE12:1;
2138 uint16_t INE13:1;
2139 uint16_t INE14:1;
2140 uint16_t INE15:1;
2141 } B;
2142 } CP1INE;
2143
2144 uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */
2145
2146 union {
2147 uint16_t R;
2148 struct {
2149 uint16_t GN0:1;
2150 uint16_t GN1:1;
2151 uint16_t GN2:1;
2152 uint16_t GN3:1;
2153 uint16_t GN4:1;
2154 uint16_t GN5:1;
2155 uint16_t GN6:1;
2156 uint16_t GN7:1;
2157 uint16_t GN8:1;
2158 uint16_t GN9:1;
2159 uint16_t GN10:1;
2160 uint16_t GN11:1;
2161 uint16_t GN12:1;
2162 uint16_t GN13:1;
2163 uint16_t GN14:1;
2164 uint16_t GN15:1;
2165 } B;
2166 } CP0NTF;
2167
2168 uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */
2169
2170 union {
2171 uint16_t R;
2172 struct {
2173 uint16_t GN0:1;
2174 uint16_t GN1:1;
2175 uint16_t GN2:1;
2176 uint16_t GN3:1;
2177 uint16_t GN4:1;
2178 uint16_t GN5:1;
2179 uint16_t GN6:1;
2180 uint16_t GN7:1;
2181 uint16_t GN8:1;
2182 uint16_t GN9:1;
2183 uint16_t GN10:1;
2184 uint16_t GN11:1;
2185 uint16_t GN12:1;
2186 uint16_t GN13:1;
2187 uint16_t GN14:1;
2188 uint16_t GN15:1;
2189 } B;
2190 } CP1NTF;
2191
2192 uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */
2193
2194 union {
2195 uint16_t R;
2196 struct {
2197 uint16_t:2;
2198 uint16_t RSTGSM:2;
2199 uint16_t:1;
2200 uint16_t RSTGMS:3;
2201 uint16_t RSTGTN:8;
2202 } B;
2203 } RSTGT;
2204
2205 uint16_t sema4_reserved6;
2206
2207 union {
2208 uint16_t R;
2209 struct {
2210 uint16_t:2;
2211 uint16_t RSTNSM:2;
2212 uint16_t:1;
2213 uint16_t RSTNMS:3;
2214 uint16_t RSTNTN:8;
2215 } B;
2216 } RSTNTF;
2217 };
2218/****************************************************************************/
2219/* MODULE : SIU */
2220/****************************************************************************/
2221 struct SIU_tag {
2222
2223 int32_t SIU_reserved0;
2224
2225 union { /* MCU ID Register */
2226 uint32_t R;
2227 struct {
2228 uint32_t PARTNUM:16;
2229 uint32_t CSP:1;
2230 uint32_t PKG:5;
2231 uint32_t:2;
2232 uint32_t MASKNUM_MAJOR:4;
2233 uint32_t MASKNUM_MINOR:4;
2234 } B;
2235 } MIDR;
2236
2237 int32_t SIU_reserved1;
2238
2239 union { /* Reset Status Register */
2240 uint32_t R;
2241 struct {
2242 uint32_t PORS:1;
2243 uint32_t ERS:1;
2244 uint32_t LLRS:1;
2245 uint32_t LCRS:1;
2246 uint32_t WDRS:1;
2247 uint32_t CRS:1;
2248 uint32_t:8;
2249 uint32_t SSRS:1;
2250 uint32_t:15;
2251 uint32_t BOOTCFG:1;
2252 uint32_t:1;
2253 } B;
2254 } RSR;
2255
2256 union { /* System Reset Control Register */
2257 uint32_t R;
2258 struct {
2259 uint32_t SSR:1;
2260 uint32_t:15;
2261 uint32_t CRE0:1;
2262 uint32_t CRE1:1;
2263 uint32_t:6;
2264 uint32_t SSRL:1;
2265 uint32_t:7;
2266 } B;
2267 } SRCR;
2268
2269 union SIU_EISR_tag { /* External Interrupt Status Register */
2270 uint32_t R;
2271 struct {
2272 uint32_t NMI0:1;
2273 uint32_t NMI1:1;
2274 uint32_t:14;
2275 uint32_t EIF15:1;
2276 uint32_t EIF14:1;
2277 uint32_t EIF13:1;
2278 uint32_t EIF12:1;
2279 uint32_t EIF11:1;
2280 uint32_t EIF10:1;
2281 uint32_t EIF9:1;
2282 uint32_t EIF8:1;
2283 uint32_t EIF7:1;
2284 uint32_t EIF6:1;
2285 uint32_t EIF5:1;
2286 uint32_t EIF4:1;
2287 uint32_t EIF3:1;
2288 uint32_t EIF2:1;
2289 uint32_t EIF1:1;
2290 uint32_t EIF0:1;
2291 } B;
2292 } EISR;
2293
2294 union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
2295 uint32_t R;
2296 struct {
2297 uint32_t:16;
2298 uint32_t EIRE15:1;
2299 uint32_t EIRE14:1;
2300 uint32_t EIRE13:1;
2301 uint32_t EIRE12:1;
2302 uint32_t EIRE11:1;
2303 uint32_t EIRE10:1;
2304 uint32_t EIRE9:1;
2305 uint32_t EIRE8:1;
2306 uint32_t EIRE7:1;
2307 uint32_t EIRE6:1;
2308 uint32_t EIRE5:1;
2309 uint32_t EIRE4:1;
2310 uint32_t EIRE3:1;
2311 uint32_t EIRE2:1;
2312 uint32_t EIRE1:1;
2313 uint32_t EIRE0:1;
2314 } B;
2315 } DIRER;
2316
2317 union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */
2318 uint32_t R;
2319 struct {
2320 uint32_t:27;
2321 uint32_t DIRS4:1;
2322 uint32_t DIRS3:1;
2323 uint32_t DIRS2:1;
2324 uint32_t DIRS1:1;
2325 uint32_t:1;
2326 } B;
2327 } DIRSR;
2328
2329 union { /* Overrun Status Register */
2330 uint32_t R;
2331 struct {
2332 uint32_t:16;
2333 uint32_t OVF15:1;
2334 uint32_t OVF14:1;
2335 uint32_t OVF13:1;
2336 uint32_t OVF12:1;
2337 uint32_t OVF11:1;
2338 uint32_t OVF10:1;
2339 uint32_t OVF9:1;
2340 uint32_t OVF8:1;
2341 uint32_t OVF7:1;
2342 uint32_t OVF6:1;
2343 uint32_t OVF5:1;
2344 uint32_t OVF4:1;
2345 uint32_t OVF3:1;
2346 uint32_t OVF2:1;
2347 uint32_t OVF1:1;
2348 uint32_t OVF0:1;
2349 } B;
2350 } OSR;
2351
2352 union SIU_ORER_tag { /* Overrun Request Enable Register */
2353 uint32_t R;
2354 struct {
2355 uint32_t:16;
2356 uint32_t ORE15:1;
2357 uint32_t ORE14:1;
2358 uint32_t ORE13:1;
2359 uint32_t ORE12:1;
2360 uint32_t ORE11:1;
2361 uint32_t ORE10:1;
2362 uint32_t ORE9:1;
2363 uint32_t ORE8:1;
2364 uint32_t ORE7:1;
2365 uint32_t ORE6:1;
2366 uint32_t ORE5:1;
2367 uint32_t ORE4:1;
2368 uint32_t ORE3:1;
2369 uint32_t ORE2:1;
2370 uint32_t ORE1:1;
2371 uint32_t ORE0:1;
2372 } B;
2373 } ORER;
2374
2375 union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
2376 uint32_t R;
2377 struct {
2378 uint32_t NREE0:1;
2379 uint32_t NREE1:1;
2380 uint32_t:14;
2381 uint32_t IREE15:1;
2382 uint32_t IREE14:1;
2383 uint32_t IREE13:1;
2384 uint32_t IREE12:1;
2385 uint32_t IREE11:1;
2386 uint32_t IREE10:1;
2387 uint32_t IREE9:1;
2388 uint32_t IREE8:1;
2389 uint32_t IREE7:1;
2390 uint32_t IREE6:1;
2391 uint32_t IREE5:1;
2392 uint32_t IREE4:1;
2393 uint32_t IREE3:1;
2394 uint32_t IREE2:1;
2395 uint32_t IREE1:1;
2396 uint32_t IREE0:1;
2397 } B;
2398 } IREER;
2399
2400 union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
2401 uint32_t R;
2402 struct {
2403 uint32_t NFEE0:1;
2404 uint32_t NFEE1:1;
2405 uint32_t:14;
2406 uint32_t IFEE15:1;
2407 uint32_t IFEE14:1;
2408 uint32_t IFEE13:1;
2409 uint32_t IFEE12:1;
2410 uint32_t IFEE11:1;
2411 uint32_t IFEE10:1;
2412 uint32_t IFEE9:1;
2413 uint32_t IFEE8:1;
2414 uint32_t IFEE7:1;
2415 uint32_t IFEE6:1;
2416 uint32_t IFEE5:1;
2417 uint32_t IFEE4:1;
2418 uint32_t IFEE3:1;
2419 uint32_t IFEE2:1;
2420 uint32_t IFEE1:1;
2421 uint32_t IFEE0:1;
2422 } B;
2423 } IFEER;
2424
2425 union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
2426 uint32_t R;
2427 struct {
2428 uint32_t:28;
2429 uint32_t DFL:4;
2430 } B;
2431 } IDFR;
2432
2433 union { /* External IRQ Filtered Input Register */
2434 uint32_t R;
2435 struct {
2436 uint32_t FNMI0:1;
2437 uint32_t FNMI1:1;
2438 uint32_t:14;
2439 uint32_t FI15:1;
2440 uint32_t FI14:1;
2441 uint32_t FI13:1;
2442 uint32_t FI12:1;
2443 uint32_t FI11:1;
2444 uint32_t FI10:1;
2445 uint32_t FI9:1;
2446 uint32_t FI8:1;
2447 uint32_t FI7:1;
2448 uint32_t FI6:1;
2449 uint32_t FI5:1;
2450 uint32_t FI4:1;
2451 uint32_t FI3:1;
2452 uint32_t FI2:1;
2453 uint32_t FI1:1;
2454 uint32_t FI0:1;
2455 } B;
2456 } IFIR;
2457
2458 int32_t SIU_reserved2[2];
2459
2460 union SIU_PCR_tag { /* Pad Configuration Registers */
2461 uint16_t R;
2462 struct {
2463 uint16_t:4;
2464 uint16_t PA:2;
2465 uint16_t OBE:1;
2466 uint16_t IBE:1;
2467 uint16_t:2;
2468 uint16_t ODE:1;
2469 uint16_t HYS:1;
2470 uint16_t SRC:2;
2471 uint16_t WPE:1;
2472 uint16_t WPS:1;
2473 } B;
2474 } PCR[146];
2475
2476 int32_t SIU_reserved3[295];
2477
2478 union { /* GPIO Pin Data Output Registers */
2479 uint8_t R;
2480 struct {
2481 uint8_t:7;
2482 uint8_t PDO:1;
2483 } B;
2484 } GPDO[146];
2485
2486 int32_t SIU_reserved4[91];
2487
2488 union { /* GPIO Pin Data Input Registers */
2489 uint8_t R;
2490 struct {
2491 uint8_t:7;
2492 uint8_t PDI:1;
2493 } B;
2494 } GPDI[146];
2495
2496 int32_t SIU_reserved5[27];
2497
2498 union { /* IMUX Register */
2499 uint32_t R;
2500 struct {
2501 uint32_t TSEL3:2;
2502 uint32_t TSEL2:2;
2503 uint32_t TSEL1:2;
2504 uint32_t TSEL0:2;
2505 uint32_t:24;
2506 } B;
2507 } ISEL0;
2508
2509 union { /* IMUX Register */
2510 uint32_t R;
2511 struct {
2512 uint32_t ESEL15:2;
2513 uint32_t ESEL14:2;
2514 uint32_t ESEL13:2;
2515 uint32_t ESEL12:2;
2516 uint32_t ESEL11:2;
2517 uint32_t ESEL10:2;
2518 uint32_t ESEL9:2;
2519 uint32_t ESEL8:2;
2520 uint32_t ESEL7:2;
2521 uint32_t ESEL6:2;
2522 uint32_t ESEL5:2;
2523 uint32_t ESEL4:2;
2524 uint32_t ESEL3:2;
2525 uint32_t ESEL2:2;
2526 uint32_t ESEL1:2;
2527 uint32_t ESEL0:2;
2528 } B;
2529 } ISEL1;
2530
2531 union { /* IMUX Register */
2532 uint32_t R;
2533 struct {
2534 uint32_t SELEMIOS15:2;
2535 uint32_t SELEMIOS14:2;
2536 uint32_t SELEMIOS13:2;
2537 uint32_t SELEMIOS12:2;
2538 uint32_t SELEMIOS11:2;
2539 uint32_t SELEMIOS10:2;
2540 uint32_t SELEMIOS9:2;
2541 uint32_t SELEMIOS8:2;
2542 uint32_t SELEMIOS7:2;
2543 uint32_t SELEMIOS6:2;
2544 uint32_t SELEMIOS5:2;
2545 uint32_t SELEMIOS4:2;
2546 uint32_t SELEMIOS3:2;
2547 uint32_t SELEMIOS2:2;
2548 uint32_t SELEMIOS1:2;
2549 uint32_t SELEMIOS0:2;
2550 } B;
2551 } ISEL2;
2552
2553 int32_t SIU_reserved6[29];
2554
2555 union { /* Chip Configuration Register Register */
2556 uint32_t R;
2557 struct {
2558 uint32_t:14;
2559 uint32_t MATCH:1;
2560 uint32_t DISNEX:1;
2561 uint32_t:16;
2562 } B;
2563 } CCR;
2564
2565 union { /* External Clock Configuration Register Register */
2566 uint32_t R;
2567 struct {
2568 uint32_t:30;
2569 uint32_t EBDF:2;
2570 } B;
2571 } ECCR;
2572
2573 union { /* Compare A High Register */
2574 uint32_t R;
2575 } CMPAH;
2576
2577 union { /* Compare A Low Register */
2578 uint32_t R;
2579 } CMPAL;
2580
2581 union { /* Compare B High Register */
2582 uint32_t R;
2583 } CMPBH;
2584
2585 union { /* Compare B Low Register */
2586 uint32_t R;
2587 } CMPBL;
2588
2589 int32_t SIU_reserved7[2];
2590
2591 union { /* System CLock Register */
2592 uint32_t R;
2593 struct {
2594 uint32_t SYSCLKSEL:2;
2595 uint32_t SYSCLKDIV:2;
2596 uint32_t SWTCLKSEL:1;
2597 uint32_t:11;
2598 uint32_t LPCLKDIV7:2;
2599 uint32_t LPCLKDIV6:2;
2600 uint32_t LPCLKDIV5:2;
2601 uint32_t LPCLKDIV4:2;
2602 uint32_t LPCLKDIV3:2;
2603 uint32_t LPCLKDIV2:2;
2604 uint32_t LPCLKDIV1:2;
2605 uint32_t LPCLKDIV0:2;
2606 } B;
2607 } SYSCLK;
2608
2609 union { /* Halt Register */
2610 uint32_t R;
2611 } HLT;
2612
2613 union { /* Halt Acknowledge Register */
2614 uint32_t R;
2615 } HLTACK;
2616
2617 int32_t SIU_reserved8[149];
2618
2619 union { /* Parallel GPIO Pin Data Output Register */
2620 uint32_t R;
2621 struct {
2622 uint32_t:16;
2623 uint32_t PB:16;
2624 } B;
2625 } PGPDO0;
2626
2627 union { /* Parallel GPIO Pin Data Output Register */
2628 uint32_t R;
2629 struct {
2630 uint32_t PC:16;
2631 uint32_t PD:16;
2632 } B;
2633 } PGPDO1;
2634
2635 union { /* Parallel GPIO Pin Data Output Register */
2636 uint32_t R;
2637 struct {
2638 uint32_t PE:16;
2639 uint32_t PF:16;
2640 } B;
2641 } PGPDO2;
2642
2643 union { /* Parallel GPIO Pin Data Output Register */
2644 uint32_t R;
2645 struct {
2646 uint32_t PG:16;
2647 uint32_t PH:16;
2648 } B;
2649 } PGPDO3;
2650
2651 union { /* Parallel GPIO Pin Data Output Register */
2652 uint32_t R;
2653 struct {
2654 uint32_t PJ:16;
2655 uint32_t:16;
2656 } B;
2657 } PGPDO4;
2658
2659 int32_t SIU_reserved9[11];
2660
2661 union { /* Parallel GPIO Pin Data Input Register */
2662 uint32_t R;
2663 struct {
2664 uint32_t PA:16;
2665 uint32_t PB:16;
2666 } B;
2667 } PGPDI0;
2668
2669 union { /* Parallel GPIO Pin Data Input Register */
2670 uint32_t R;
2671 struct {
2672 uint32_t PC:16;
2673 uint32_t PD:16;
2674 } B;
2675 } PGPDI1;
2676
2677 union { /* Parallel GPIO Pin Data Input Register */
2678 uint32_t R;
2679 struct {
2680 uint32_t PE:16;
2681 uint32_t PF:16;
2682 } B;
2683 } PGPDI2;
2684
2685 union { /* Parallel GPIO Pin Data Input Register */
2686 uint32_t R;
2687 struct {
2688 uint32_t PG:16;
2689 uint32_t PH:16;
2690 } B;
2691 } PGPDI3;
2692
2693 union { /* Parallel GPIO Pin Data Input Register */
2694 uint32_t R;
2695 struct {
2696 uint32_t PJ:16;
2697 uint32_t PK:2;
2698 uint32_t:14;
2699 } B;
2700 } PGPDI4;
2701
2702 int32_t SIU_reserved10[12];
2703
2704 union { /* Masked Parallel GPIO Pin Data Input Register */
2705 uint32_t R;
2706 struct {
2707 uint32_t PB_MASK:16;
2708 uint32_t PB:16;
2709 } B;
2710 } MPGPDO1;
2711
2712 union { /* Masked Parallel GPIO Pin Data Input Register */
2713 uint32_t R;
2714 struct {
2715 uint32_t PC_MASK:16;
2716 uint32_t PC:16;
2717 } B;
2718 } MPGPDO2;
2719
2720 union { /* Masked Parallel GPIO Pin Data Input Register */
2721 uint32_t R;
2722 struct {
2723 uint32_t PD_MASK:16;
2724 uint32_t PD:16;
2725 } B;
2726 } MPGPDO3;
2727
2728 union { /* Masked Parallel GPIO Pin Data Input Register */
2729 uint32_t R;
2730 struct {
2731 uint32_t PE_MASK:16;
2732 uint32_t PE:16;
2733 } B;
2734 } MPGPDO4;
2735
2736 union { /* Masked Parallel GPIO Pin Data Input Register */
2737 uint32_t R;
2738 struct {
2739 uint32_t PF_MASK:16;
2740 uint32_t PF:16;
2741 } B;
2742 } MPGPDO5;
2743
2744 union { /* Masked Parallel GPIO Pin Data Input Register */
2745 uint32_t R;
2746 struct {
2747 uint32_t PG_MASK:16;
2748 uint32_t PG:16;
2749 } B;
2750 } MPGPDO6;
2751
2752 union { /* Masked Parallel GPIO Pin Data Input Register */
2753 uint32_t R;
2754 struct {
2755 uint32_t PH_MASK:16;
2756 uint32_t PH:16;
2757 } B;
2758 } MPGPDO7;
2759
2760 union { /* Masked Parallel GPIO Pin Data Input Register */
2761 uint32_t R;
2762 struct {
2763 uint32_t PJ_MASK:16;
2764 uint32_t PJ:16;
2765 } B;
2766 } MPGPDO8;
2767
2768 };
2769/****************************************************************************/
2770/* MODULE : FlexRay */
2771/****************************************************************************/
2772
2773 typedef union uMVR {
2774 uint16_t R;
2775 struct {
2776 uint16_t CHIVER:8; /* CHI Version Number */
2777 uint16_t PEVER:8; /* PE Version Number */
2778 } B;
2779 } MVR_t;
2780
2781 typedef union uMCR {
2782 uint16_t R;
2783 struct {
2784 uint16_t MEN:1; /* module enable */
2785 uint16_t:1;
2786 uint16_t SCMD:1; /* single channel mode */
2787 uint16_t CHB:1; /* channel B enable */
2788 uint16_t CHA:1; /* channel A enable */
2789 uint16_t SFFE:1; /* synchronization frame filter enable */
2790 uint16_t:5;
2791 uint16_t CLKSEL:1; /* protocol engine clock source select */
2792 uint16_t PRESCALE:3; /* protocol engine clock prescaler */
2793 uint16_t:1;
2794 } B;
2795 } MCR_t;
2796 typedef union uSTBSCR {
2797 uint16_t R;
2798 struct {
2799 uint16_t WMD:1; /* write mode */
2800 uint16_t STBSSEL:7; /* strobe signal select */
2801 uint16_t:3;
2802 uint16_t ENB:1; /* strobe signal enable */
2803 uint16_t:2;
2804 uint16_t STBPSEL:2; /* strobe port select */
2805 } B;
2806 } STBSCR_t;
2807 typedef union uMBDSR {
2808 uint16_t R;
2809 struct {
2810 uint16_t:1;
2811 uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
2812 uint16_t:1;
2813 uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
2814 } B;
2815 } MBDSR_t;
2816
2817 typedef union uMBSSUTR {
2818 uint16_t R;
2819 struct {
2820
2821 uint16_t:2;
2822 uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */
2823 uint16_t:2;
2824 uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */
2825 } B;
2826 } MBSSUTR_t;
2827
2828 typedef union uPOCR {
2829 uint16_t R;
2830 uint8_t byte[2];
2831 struct {
2832 uint16_t WME:1; /* write mode external correction command */
2833 uint16_t:3;
2834 uint16_t EOC_AP:2; /* external offset correction application */
2835 uint16_t ERC_AP:2; /* external rate correction application */
2836 uint16_t BSY:1; /* command write busy / write mode command */
2837 uint16_t:3;
2838 uint16_t POCCMD:4; /* protocol command */
2839 } B;
2840 } POCR_t;
2841/* protocol commands */
2842 typedef union uGIFER {
2843 uint16_t R;
2844 struct {
2845 uint16_t MIF:1; /* module interrupt flag */
2846 uint16_t PRIF:1; /* protocol interrupt flag */
2847 uint16_t CHIF:1; /* CHI interrupt flag */
2848 uint16_t WKUPIF:1; /* wakeup interrupt flag */
2849 uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
2850 uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
2851 uint16_t RBIF:1; /* receive message buffer interrupt flag */
2852 uint16_t TBIF:1; /* transmit buffer interrupt flag */
2853 uint16_t MIE:1; /* module interrupt enable */
2854 uint16_t PRIE:1; /* protocol interrupt enable */
2855 uint16_t CHIE:1; /* CHI interrupt enable */
2856 uint16_t WKUPIE:1; /* wakeup interrupt enable */
2857 uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
2858 uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
2859 uint16_t RBIE:1; /* receive message buffer interrupt enable */
2860 uint16_t TBIE:1; /* transmit buffer interrupt enable */
2861 } B;
2862 } GIFER_t;
2863 typedef union uPIFR0 {
2864 uint16_t R;
2865 struct {
2866 uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
2867 uint16_t INTLIF:1; /* internal protocol error interrupt flag */
2868 uint16_t ILCFIF:1; /* illegal protocol configuration flag */
2869 uint16_t CSAIF:1; /* cold start abort interrupt flag */
2870 uint16_t MRCIF:1; /* missing rate correctio interrupt flag */
2871 uint16_t MOCIF:1; /* missing offset correctio interrupt flag */
2872 uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
2873 uint16_t MXSIF:1; /* max sync frames detected interrupt flag */
2874 uint16_t MTXIF:1; /* media access test symbol received flag */
2875 uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
2876 uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
2877 uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
2878 uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
2879 uint16_t TI2IF:1; /* timer 2 expired interrupt flag */
2880 uint16_t TI1IF:1; /* timer 1 expired interrupt flag */
2881 uint16_t CYSIF:1; /* cycle start interrupt flag */
2882 } B;
2883 } PIFR0_t;
2884 typedef union uPIFR1 {
2885 uint16_t R;
2886 struct {
2887 uint16_t EMCIF:1; /* error mode changed interrupt flag */
2888 uint16_t IPCIF:1; /* illegal protocol command interrupt flag */
2889 uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
2890 uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
2891 uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
2892 uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
2893 uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
2894 uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
2895 uint16_t:2;
2896 uint16_t EVTIF:1; /* even cycle table written interrupt flag */
2897 uint16_t ODTIF:1; /* odd cycle table written interrupt flag */
2898 uint16_t:4;
2899 } B;
2900 } PIFR1_t;
2901 typedef union uPIER0 {
2902 uint16_t R;
2903 struct {
2904 uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
2905 uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
2906 uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
2907 uint16_t CSAIE:1; /* cold start abort interrupt enable */
2908 uint16_t MRCIE:1; /* missing rate correctio interrupt enable */
2909 uint16_t MOCIE:1; /* missing offset correctio interrupt enable */
2910 uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
2911 uint16_t MXSIE:1; /* max sync frames detected interrupt enable */
2912 uint16_t MTXIE:1; /* media access test symbol received interrupt enable */
2913 uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
2914 uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
2915 uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
2916 uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
2917 uint16_t TI2IE:1; /* timer 2 expired interrupt enable */
2918 uint16_t TI1IE:1; /* timer 1 expired interrupt enable */
2919 uint16_t CYSIE:1; /* cycle start interrupt enable */
2920 } B;
2921 } PIER0_t;
2922 typedef union uPIER1 {
2923 uint16_t R;
2924 struct {
2925 uint16_t EMCIE:1; /* error mode changed interrupt enable */
2926 uint16_t IPCIE:1; /* illegal protocol command interrupt enable */
2927 uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
2928 uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
2929 uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
2930 uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
2931 uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
2932 uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
2933 uint16_t:2;
2934 uint16_t EVTIE:1; /* even cycle table written interrupt enable */
2935 uint16_t ODTIE:1; /* odd cycle table written interrupt enable */
2936 uint16_t:4;
2937 } B;
2938 } PIER1_t;
2939 typedef union uCHIERFR {
2940 uint16_t R;
2941 struct {
2942 uint16_t FRLBEF:1; /* flame lost channel B error flag */
2943 uint16_t FRLAEF:1; /* frame lost channel A error flag */
2944 uint16_t PCMIEF:1; /* command ignored error flag */
2945 uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
2946 uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
2947 uint16_t MSBEF:1; /* message buffer search error flag */
2948 uint16_t MBUEF:1; /* message buffer utilization error flag */
2949 uint16_t LCKEF:1; /* lock error flag */
2950 uint16_t DBLEF:1; /* double transmit message buffer lock error flag */
2951 uint16_t SBCFEF:1; /* system bus communication failure error flag */
2952 uint16_t FIDEF:1; /* frame ID error flag */
2953 uint16_t DPLEF:1; /* dynamic payload length error flag */
2954 uint16_t SPLEF:1; /* static payload length error flag */
2955 uint16_t NMLEF:1; /* network management length error flag */
2956 uint16_t NMFEF:1; /* network management frame error flag */
2957 uint16_t ILSAEF:1; /* illegal access error flag */
2958 } B;
2959 } CHIERFR_t;
2960 typedef union uMBIVEC {
2961 uint16_t R;
2962 struct {
2963
2964 uint16_t:2;
2965 uint16_t TBIVEC:6; /* transmit buffer interrupt vector */
2966 uint16_t:2;
2967 uint16_t RBIVEC:6; /* receive buffer interrupt vector */
2968 } B;
2969 } MBIVEC_t;
2970
2971 typedef union uPSR0 {
2972 uint16_t R;
2973 struct {
2974 uint16_t ERRMODE:2; /* error mode */
2975 uint16_t SLOTMODE:2; /* slot mode */
2976 uint16_t:1;
2977 uint16_t PROTSTATE:3; /* protocol state */
2978 uint16_t SUBSTATE:4; /* protocol sub state */
2979 uint16_t:1;
2980 uint16_t WAKEUPSTATUS:3; /* wakeup status */
2981 } B;
2982 } PSR0_t;
2983
2984/* protocol states */
2985/* protocol sub-states */
2986/* wakeup status */
2987 typedef union uPSR1 {
2988 uint16_t R;
2989 struct {
2990 uint16_t CSAA:1; /* cold start attempt abort flag */
2991 uint16_t SCP:1; /* cold start path */
2992 uint16_t:1;
2993 uint16_t REMCSAT:5; /* remanining coldstart attempts */
2994 uint16_t CPN:1; /* cold start noise path */
2995 uint16_t HHR:1; /* host halt request pending */
2996 uint16_t FRZ:1; /* freeze occured */
2997 uint16_t APTAC:5; /* allow passive to active counter */
2998 } B;
2999 } PSR1_t;
3000 typedef union uPSR2 {
3001 uint16_t R;
3002 struct {
3003 uint16_t NBVB:1; /* NIT boundary violation on channel B */
3004 uint16_t NSEB:1; /* NIT syntax error on channel B */
3005 uint16_t STCB:1; /* symbol window transmit conflict on channel B */
3006 uint16_t SBVB:1; /* symbol window boundary violation on channel B */
3007 uint16_t SSEB:1; /* symbol window syntax error on channel B */
3008 uint16_t MTB:1; /* media access test symbol MTS received on channel B */
3009 uint16_t NBVA:1; /* NIT boundary violation on channel A */
3010 uint16_t NSEA:1; /* NIT syntax error on channel A */
3011 uint16_t STCA:1; /* symbol window transmit conflict on channel A */
3012 uint16_t SBVA:1; /* symbol window boundary violation on channel A */
3013 uint16_t SSEA:1; /* symbol window syntax error on channel A */
3014 uint16_t MTA:1; /* media access test symbol MTS received on channel A */
3015 uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
3016 } B;
3017 } PSR2_t;
3018 typedef union uPSR3 {
3019 uint16_t R;
3020 struct {
3021 uint16_t:2;
3022 uint16_t WUB:1; /* wakeup symbol received on channel B */
3023 uint16_t ABVB:1; /* aggregated boundary violation on channel B */
3024 uint16_t AACB:1; /* aggregated additional communication on channel B */
3025 uint16_t ACEB:1; /* aggregated content error on channel B */
3026 uint16_t ASEB:1; /* aggregated syntax error on channel B */
3027 uint16_t AVFB:1; /* aggregated valid frame on channel B */
3028 uint16_t:2;
3029 uint16_t WUA:1; /* wakeup symbol received on channel A */
3030 uint16_t ABVA:1; /* aggregated boundary violation on channel A */
3031 uint16_t AACA:1; /* aggregated additional communication on channel A */
3032 uint16_t ACEA:1; /* aggregated content error on channel A */
3033 uint16_t ASEA:1; /* aggregated syntax error on channel A */
3034 uint16_t AVFA:1; /* aggregated valid frame on channel A */
3035 } B;
3036 } PSR3_t;
3037 typedef union uCIFRR {
3038 uint16_t R;
3039 struct {
3040 uint16_t:8;
3041 uint16_t MIFR:1; /* module interrupt flag */
3042 uint16_t PRIFR:1; /* protocol interrupt flag */
3043 uint16_t CHIFR:1; /* CHI interrupt flag */
3044 uint16_t WUPIFR:1; /* wakeup interrupt flag */
3045 uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
3046 uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
3047 uint16_t RBIFR:1; /* receive message buffer interrupt flag */
3048 uint16_t TBIFR:1; /* transmit buffer interrupt flag */
3049 } B;
3050 } CIFRR_t;
3051 typedef union uSYMATOR {
3052 uint16_t R;
3053 struct {
3054 uint16_t:11;
3055 uint16_t TIMEOUT:5; /* system memory time out value */
3056 } B;
3057 } SYMATOR_t;
3058
3059 typedef union uSFCNTR {
3060 uint16_t R;
3061 struct {
3062 uint16_t SFEVB:4; /* sync frames channel B, even cycle */
3063 uint16_t SFEVA:4; /* sync frames channel A, even cycle */
3064 uint16_t SFODB:4; /* sync frames channel B, odd cycle */
3065 uint16_t SFODA:4; /* sync frames channel A, odd cycle */
3066 } B;
3067 } SFCNTR_t;
3068
3069 typedef union uSFTCCSR {
3070 uint16_t R;
3071 struct {
3072 uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
3073 uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
3074 uint16_t CYCNUM:6; /* cycle number */
3075 uint16_t ELKS:1; /* even cycle tables lock status */
3076 uint16_t OLKS:1; /* odd cycle tables lock status */
3077 uint16_t EVAL:1; /* even cycle tables valid */
3078 uint16_t OVAL:1; /* odd cycle tables valid */
3079 uint16_t:1;
3080 uint16_t OPT:1; /*one pair trigger */
3081 uint16_t SDVEN:1; /* sync frame deviation table enable */
3082 uint16_t SIDEN:1; /* sync frame ID table enable */
3083 } B;
3084 } SFTCCSR_t;
3085 typedef union uSFIDRFR {
3086 uint16_t R;
3087 struct {
3088 uint16_t:6;
3089 uint16_t SYNFRID:10; /* sync frame rejection ID */
3090 } B;
3091 } SFIDRFR_t;
3092
3093 typedef union uTICCR {
3094 uint16_t R;
3095 struct {
3096 uint16_t:2;
3097 uint16_t T2CFG:1; /* timer 2 configuration */
3098 uint16_t T2REP:1; /* timer 2 repetitive mode */
3099 uint16_t:1;
3100 uint16_t T2SP:1; /* timer 2 stop */
3101 uint16_t T2TR:1; /* timer 2 trigger */
3102 uint16_t T2ST:1; /* timer 2 state */
3103 uint16_t:3;
3104 uint16_t T1REP:1; /* timer 1 repetitive mode */
3105 uint16_t:1;
3106 uint16_t T1SP:1; /* timer 1 stop */
3107 uint16_t T1TR:1; /* timer 1 trigger */
3108 uint16_t T1ST:1; /* timer 1 state */
3109
3110 } B;
3111 } TICCR_t;
3112 typedef union uTI1CYSR {
3113 uint16_t R;
3114 struct {
3115 uint16_t:2;
3116 uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
3117 uint16_t:2;
3118 uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
3119
3120 } B;
3121 } TI1CYSR_t;
3122
3123 typedef union uSSSR {
3124 uint16_t R;
3125 struct {
3126 uint16_t WMD:1; /* write mode */
3127 uint16_t:1;
3128 uint16_t SEL:2; /* static slot number */
3129 uint16_t:1;
3130 uint16_t SLOTNUMBER:11; /* selector */
3131 } B;
3132 } SSSR_t;
3133
3134 typedef union uSSCCR {
3135 uint16_t R;
3136 struct {
3137 uint16_t WMD:1; /* write mode */
3138 uint16_t:1;
3139 uint16_t SEL:2; /* selector */
3140 uint16_t:1;
3141 uint16_t CNTCFG:2; /* counter configuration */
3142 uint16_t MCY:1; /* multi cycle selection */
3143 uint16_t VFR:1; /* valid frame selection */
3144 uint16_t SYF:1; /* sync frame selection */
3145 uint16_t NUF:1; /* null frame selection */
3146 uint16_t SUF:1; /* startup frame selection */
3147 uint16_t STATUSMASK:4; /* slot status mask */
3148 } B;
3149 } SSCCR_t;
3150 typedef union uSSR {
3151 uint16_t R;
3152 struct {
3153 uint16_t VFB:1; /* valid frame on channel B */
3154 uint16_t SYB:1; /* valid sync frame on channel B */
3155 uint16_t NFB:1; /* valid null frame on channel B */
3156 uint16_t SUB:1; /* valid startup frame on channel B */
3157 uint16_t SEB:1; /* syntax error on channel B */
3158 uint16_t CEB:1; /* content error on channel B */
3159 uint16_t BVB:1; /* boundary violation on channel B */
3160 uint16_t TCB:1; /* tx conflict on channel B */
3161 uint16_t VFA:1; /* valid frame on channel A */
3162 uint16_t SYA:1; /* valid sync frame on channel A */
3163 uint16_t NFA:1; /* valid null frame on channel A */
3164 uint16_t SUA:1; /* valid startup frame on channel A */
3165 uint16_t SEA:1; /* syntax error on channel A */
3166 uint16_t CEA:1; /* content error on channel A */
3167 uint16_t BVA:1; /* boundary violation on channel A */
3168 uint16_t TCA:1; /* tx conflict on channel A */
3169 } B;
3170 } SSR_t;
3171 typedef union uMTSCFR {
3172 uint16_t R;
3173 struct {
3174 uint16_t MTE:1; /* media access test symbol transmission enable */
3175 uint16_t:1;
3176 uint16_t CYCCNTMSK:6; /* cycle counter mask */
3177 uint16_t:2;
3178 uint16_t CYCCNTVAL:6; /* cycle counter value */
3179 } B;
3180 } MTSCFR_t;
3181
3182 typedef union uRSBIR {
3183 uint16_t R;
3184 struct {
3185 uint16_t WMD:1; /* write mode */
3186 uint16_t:1;
3187 uint16_t SEL:2; /* selector */
3188 uint16_t:5;
3189 uint16_t RSBIDX:7; /* receive shadow buffer index */
3190 } B;
3191 } RSBIR_t;
3192
3193 typedef union uRFDSR {
3194 uint16_t R;
3195 struct {
3196 uint16_t FIFODEPTH:8; /* fifo depth */
3197 uint16_t:1;
3198 uint16_t ENTRYSIZE:7; /* entry size */
3199 } B;
3200 } RFDSR_t;
3201
3202 typedef union uRFRFCFR {
3203 uint16_t R;
3204 struct {
3205 uint16_t WMD:1; /* write mode */
3206 uint16_t IBD:1; /* interval boundary */
3207 uint16_t SEL:2; /* filter number */
3208 uint16_t:1;
3209 uint16_t SID:11; /* slot ID */
3210 } B;
3211 } RFRFCFR_t;
3212
3213 typedef union uRFRFCTR {
3214 uint16_t R;
3215 struct {
3216 uint16_t:4;
3217 uint16_t F3MD:1; /* filter mode */
3218 uint16_t F2MD:1; /* filter mode */
3219 uint16_t F1MD:1; /* filter mode */
3220 uint16_t F0MD:1; /* filter mode */
3221 uint16_t:4;
3222 uint16_t F3EN:1; /* filter enable */
3223 uint16_t F2EN:1; /* filter enable */
3224 uint16_t F1EN:1; /* filter enable */
3225 uint16_t F0EN:1; /* filter enable */
3226 } B;
3227 } RFRFCTR_t;
3228 typedef union uPCR0 {
3229 uint16_t R;
3230 struct {
3231 uint16_t ACTION_POINT_OFFSET:6;
3232 uint16_t STATIC_SLOT_LENGTH:10;
3233 } B;
3234 } PCR0_t;
3235
3236 typedef union uPCR1 {
3237 uint16_t R;
3238 struct {
3239 uint16_t:2;
3240 uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3241 } B;
3242 } PCR1_t;
3243
3244 typedef union uPCR2 {
3245 uint16_t R;
3246 struct {
3247 uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3248 uint16_t NUMBER_OF_STATIC_SLOTS:10;
3249 } B;
3250 } PCR2_t;
3251
3252 typedef union uPCR3 {
3253 uint16_t R;
3254 struct {
3255 uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3256 uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3257 uint16_t COLDSTART_ATTEMPTS:5;
3258 } B;
3259 } PCR3_t;
3260
3261 typedef union uPCR4 {
3262 uint16_t R;
3263 struct {
3264 uint16_t CAS_RX_LOW_MAX:7;
3265 uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3266 } B;
3267 } PCR4_t;
3268
3269 typedef union uPCR5 {
3270 uint16_t R;
3271 struct {
3272 uint16_t TSS_TRANSMITTER:4;
3273 uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3274 uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3275 } B;
3276 } PCR5_t;
3277
3278 typedef union uPCR6 {
3279 uint16_t R;
3280 struct {
3281 uint16_t:1;
3282 uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3283 uint16_t MACRO_INITIAL_OFFSET_A:7;
3284 } B;
3285 } PCR6_t;
3286
3287 typedef union uPCR7 {
3288 uint16_t R;
3289 struct {
3290 uint16_t DECODING_CORRECTION_B:9;
3291 uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3292 } B;
3293 } PCR7_t;
3294
3295 typedef union uPCR8 {
3296 uint16_t R;
3297 struct {
3298 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3299 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3300 uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3301 } B;
3302 } PCR8_t;
3303
3304 typedef union uPCR9 {
3305 uint16_t R;
3306 struct {
3307 uint16_t MINISLOT_EXISTS:1;
3308 uint16_t SYMBOL_WINDOW_EXISTS:1;
3309 uint16_t OFFSET_CORRECTION_OUT:14;
3310 } B;
3311 } PCR9_t;
3312
3313 typedef union uPCR10 {
3314 uint16_t R;
3315 struct {
3316 uint16_t SINGLE_SLOT_ENABLED:1;
3317 uint16_t WAKEUP_CHANNEL:1;
3318 uint16_t MACRO_PER_CYCLE:14;
3319 } B;
3320 } PCR10_t;
3321
3322 typedef union uPCR11 {
3323 uint16_t R;
3324 struct {
3325 uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
3326 uint16_t KEY_SLOT_USED_FOR_SYNC:1;
3327 uint16_t OFFSET_CORRECTION_START:14;
3328 } B;
3329 } PCR11_t;
3330
3331 typedef union uPCR12 {
3332 uint16_t R;
3333 struct {
3334 uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
3335 uint16_t KEY_SLOT_HEADER_CRC:11;
3336 } B;
3337 } PCR12_t;
3338
3339 typedef union uPCR13 {
3340 uint16_t R;
3341 struct {
3342 uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
3343 uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
3344 } B;
3345 } PCR13_t;
3346
3347 typedef union uPCR14 {
3348 uint16_t R;
3349 struct {
3350 uint16_t RATE_CORRECTION_OUT:11;
3351 uint16_t LISTEN_TIMEOUT_H:5;
3352 } B;
3353 } PCR14_t;
3354
3355 typedef union uPCR15 {
3356 uint16_t R;
3357 struct {
3358 uint16_t LISTEN_TIMEOUT_L:16;
3359 } B;
3360 } PCR15_t;
3361
3362 typedef union uPCR16 {
3363 uint16_t R;
3364 struct {
3365 uint16_t MACRO_INITIAL_OFFSET_B:7;
3366 uint16_t NOISE_LISTEN_TIMEOUT_H:9;
3367 } B;
3368 } PCR16_t;
3369
3370 typedef union uPCR17 {
3371 uint16_t R;
3372 struct {
3373 uint16_t NOISE_LISTEN_TIMEOUT_L:16;
3374 } B;
3375 } PCR17_t;
3376
3377 typedef union uPCR18 {
3378 uint16_t R;
3379 struct {
3380 uint16_t WAKEUP_PATTERN:6;
3381 uint16_t KEY_SLOT_ID:10;
3382 } B;
3383 } PCR18_t;
3384
3385 typedef union uPCR19 {
3386 uint16_t R;
3387 struct {
3388 uint16_t DECODING_CORRECTION_A:9;
3389 uint16_t PAYLOAD_LENGTH_STATIC:7;
3390 } B;
3391 } PCR19_t;
3392
3393 typedef union uPCR20 {
3394 uint16_t R;
3395 struct {
3396 uint16_t MICRO_INITIAL_OFFSET_B:8;
3397 uint16_t MICRO_INITIAL_OFFSET_A:8;
3398 } B;
3399 } PCR20_t;
3400
3401 typedef union uPCR21 {
3402 uint16_t R;
3403 struct {
3404 uint16_t EXTERN_RATE_CORRECTION:3;
3405 uint16_t LATEST_TX:13;
3406 } B;
3407 } PCR21_t;
3408
3409 typedef union uPCR22 {
3410 uint16_t R;
3411 struct {
3412 uint16_t:1;
3413 uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
3414 uint16_t MICRO_PER_CYCLE_H:4;
3415 } B;
3416 } PCR22_t;
3417
3418 typedef union uPCR23 {
3419 uint16_t R;
3420 struct {
3421 uint16_t micro_per_cycle_l:16;
3422 } B;
3423 } PCR23_t;
3424
3425 typedef union uPCR24 {
3426 uint16_t R;
3427 struct {
3428 uint16_t CLUSTER_DRIFT_DAMPING:5;
3429 uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
3430 uint16_t MICRO_PER_CYCLE_MIN_H:4;
3431 } B;
3432 } PCR24_t;
3433
3434 typedef union uPCR25 {
3435 uint16_t R;
3436 struct {
3437 uint16_t MICRO_PER_CYCLE_MIN_L:16;
3438 } B;
3439 } PCR25_t;
3440
3441 typedef union uPCR26 {
3442 uint16_t R;
3443 struct {
3444 uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
3445 uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
3446 uint16_t MICRO_PER_CYCLE_MAX_H:4;
3447 } B;
3448 } PCR26_t;
3449
3450 typedef union uPCR27 {
3451 uint16_t R;
3452 struct {
3453 uint16_t MICRO_PER_CYCLE_MAX_L:16;
3454 } B;
3455 } PCR27_t;
3456
3457 typedef union uPCR28 {
3458 uint16_t R;
3459 struct {
3460 uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
3461 uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
3462 } B;
3463 } PCR28_t;
3464
3465 typedef union uPCR29 {
3466 uint16_t R;
3467 struct {
3468 uint16_t EXTERN_OFFSET_CORRECTION:3;
3469 uint16_t MINISLOTS_MAX:13;
3470 } B;
3471 } PCR29_t;
3472
3473 typedef union uPCR30 {
3474 uint16_t R;
3475 struct {
3476 uint16_t:12;
3477 uint16_t SYNC_NODE_MAX:4;
3478 } B;
3479 } PCR30_t;
3480
3481 typedef struct uMSG_BUFF_CCS {
3482 union {
3483 uint16_t R;
3484 struct {
3485 uint16_t:1;
3486 uint16_t MCM:1; /* message buffer commit mode */
3487 uint16_t MBT:1; /* message buffer type */
3488 uint16_t MTD:1; /* message buffer direction */
3489 uint16_t CMT:1; /* commit for transmission */
3490 uint16_t EDT:1; /* enable / disable trigger */
3491 uint16_t LCKT:1; /* lock request trigger */
3492 uint16_t MBIE:1; /* message buffer interrupt enable */
3493 uint16_t:3;
3494 uint16_t DUP:1; /* data updated */
3495 uint16_t DVAL:1; /* data valid */
3496 uint16_t EDS:1; /* lock status */
3497 uint16_t LCKS:1; /* enable / disable status */
3498 uint16_t MBIF:1; /* message buffer interrupt flag */
3499 } B;
3500 } MBCCSR;
3501 union {
3502 uint16_t R;
3503 struct {
3504 uint16_t MTM:1; /* message buffer transmission mode */
3505 uint16_t CHNLA:1; /* channel assignement */
3506 uint16_t CHNLB:1; /* channel assignement */
3507 uint16_t CCFE:1; /* cycle counter filter enable */
3508 uint16_t CCFMSK:6; /* cycle counter filter mask */
3509 uint16_t CCFVAL:6; /* cycle counter filter value */
3510 } B;
3511 } MBCCFR;
3512 union {
3513 uint16_t R;
3514 struct {
3515 uint16_t:5;
3516 uint16_t FID:11; /* frame ID */
3517 } B;
3518 } MBFIDR;
3519
3520 union {
3521 uint16_t R;
3522 struct {
3523 uint16_t:9;
3524 uint16_t MBIDX:7; /* message buffer index */
3525 } B;
3526 } MBIDXR;
3527 } MSG_BUFF_CCS_t;
3528 typedef union uSYSBADHR {
3529 uint16_t R;
3530 } SYSBADHR_t;
3531 typedef union uSYSBADLR {
3532 uint16_t R;
3533 } SYSBADLR_t;
3534 typedef union uPADR {
3535 uint16_t R;
3536 } PADR_t;
3537 typedef union uPDAR {
3538 uint16_t R;
3539 } PDAR_t;
3540 typedef union uCASERCR {
3541 uint16_t R;
3542 } CASERCR_t;
3543 typedef union uCBSERCR {
3544 uint16_t R;
3545 } CBSERCR_t;
3546 typedef union uCYCTR {
3547 uint16_t R;
3548 } CYCTR_t;
3549 typedef union uMTCTR {
3550 uint16_t R;
3551 } MTCTR_t;
3552 typedef union uSLTCTAR {
3553 uint16_t R;
3554 } SLTCTAR_t;
3555 typedef union uSLTCTBR {
3556 uint16_t R;
3557 } SLTCTBR_t;
3558 typedef union uRTCORVR {
3559 uint16_t R;
3560 } RTCORVR_t;
3561 typedef union uOFCORVR {
3562 uint16_t R;
3563 } OFCORVR_t;
3564 typedef union uSFTOR {
3565 uint16_t R;
3566 } SFTOR_t;
3567 typedef union uSFIDAFVR {
3568 uint16_t R;
3569 } SFIDAFVR_t;
3570 typedef union uSFIDAFMR {
3571 uint16_t R;
3572 } SFIDAFMR_t;
3573 typedef union uNMVR {
3574 uint16_t R;
3575 } NMVR_t;
3576 typedef union uNMVLR {
3577 uint16_t R;
3578 } NMVLR_t;
3579 typedef union uT1MTOR {
3580 uint16_t R;
3581 } T1MTOR_t;
3582 typedef union uTI2CR0 {
3583 uint16_t R;
3584 } TI2CR0_t;
3585 typedef union uTI2CR1 {
3586 uint16_t R;
3587 } TI2CR1_t;
3588 typedef union uSSCR {
3589 uint16_t R;
3590 } SSCR_t;
3591 typedef union uRFSR {
3592 uint16_t R;
3593 } RFSR_t;
3594 typedef union uRFSIR {
3595 uint16_t R;
3596 } RFSIR_t;
3597 typedef union uRFARIR {
3598 uint16_t R;
3599 } RFARIR_t;
3600 typedef union uRFBRIR {
3601 uint16_t R;
3602 } RFBRIR_t;
3603 typedef union uRFMIDAFVR {
3604 uint16_t R;
3605 } RFMIDAFVR_t;
3606 typedef union uRFMIAFMR {
3607 uint16_t R;
3608 } RFMIAFMR_t;
3609 typedef union uRFFIDRFVR {
3610 uint16_t R;
3611 } RFFIDRFVR_t;
3612 typedef union uRFFIDRFMR {
3613 uint16_t R;
3614 } RFFIDRFMR_t;
3615 typedef union uLDTXSLAR {
3616 uint16_t R;
3617 } LDTXSLAR_t;
3618 typedef union uLDTXSLBR {
3619 uint16_t R;
3620 } LDTXSLBR_t;
3621
3622 typedef struct FR_tag {
3623 volatile MVR_t MVR; /*module version register *//*0 */
3624 volatile MCR_t MCR; /*module configuration register *//*2 */
3625 volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
3626 volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
3627 volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
3628 uint16_t reserved0[1]; /*A */
3629 volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
3630 volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
3631 uint16_t reserved1[1]; /*10 */
3632 uint16_t reserved2[1]; /*12 */
3633 volatile POCR_t POCR; /*Protocol operation control register *//*14 */
3634 volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
3635 volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
3636 volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
3637 volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
3638 volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
3639 volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
3640 volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
3641 volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
3642 volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
3643 volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
3644 volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
3645 volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
3646 volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
3647 volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
3648 volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
3649 volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
3650 volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
3651 volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
3652 volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
3653 volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
3654 volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */
3655 volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
3656 volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
3657 volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
3658 volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
3659 volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
3660 volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
3661 volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
3662 volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
3663 volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
3664 volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
3665 volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
3666 volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
3667 volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
3668 volatile SSSR_t SSSR; /*slot status selection register *//*64 */
3669 volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
3670 volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
3671 volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
3672 volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
3673 volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
3674 volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
3675 volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
3676 volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
3677 volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
3678 volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
3679 volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
3680 volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
3681 volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
3682 volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
3683 volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
3684 volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
3685 volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
3686 volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
3687 volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
3688 volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
3689 volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
3690 volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
3691 volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
3692 volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
3693 volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
3694 volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
3695 volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
3696 volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
3697 volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
3698 volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
3699 volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
3700 volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
3701 volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
3702 volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
3703 volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
3704 volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
3705 volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
3706 volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
3707 volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
3708 volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
3709 volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
3710 volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
3711 volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
3712 volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
3713 volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
3714 volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
3715 volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
3716 volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
3717 volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
3718 volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
3719 uint16_t reserved3[17];
3720 volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
3721 } FR_tag_t;
3722
3723 typedef union uF_HEADER /* frame header */
3724 {
3725 struct {
3726 uint16_t:5;
3727 uint16_t HDCRC:11; /* Header CRC */
3728 uint16_t:2;
3729 uint16_t CYCCNT:6; /* Cycle Count */
3730 uint16_t:1;
3731 uint16_t PLDLEN:7; /* Payload Length */
3732 uint16_t:1;
3733 uint16_t PPI:1; /* Payload Preamble Indicator */
3734 uint16_t NUF:1; /* Null Frame Indicator */
3735 uint16_t SYF:1; /* Sync Frame Indicator */
3736 uint16_t SUF:1; /* Startup Frame Indicator */
3737 uint16_t FID:11; /* Frame ID */
3738 } B;
3739 uint16_t WORDS[3];
3740 } F_HEADER_t;
3741 typedef union uS_STSTUS /* slot status */
3742 {
3743 struct {
3744 uint16_t VFB:1; /* Valid Frame on channel B */
3745 uint16_t SYB:1; /* Sync Frame Indicator channel B */
3746 uint16_t NFB:1; /* Null Frame Indicator channel B */
3747 uint16_t SUB:1; /* Startup Frame Indicator channel B */
3748 uint16_t SEB:1; /* Syntax Error on channel B */
3749 uint16_t CEB:1; /* Content Error on channel B */
3750 uint16_t BVB:1; /* Boundary Violation on channel B */
3751 uint16_t CH:1; /* Channel */
3752 uint16_t VFA:1; /* Valid Frame on channel A */
3753 uint16_t SYA:1; /* Sync Frame Indicator channel A */
3754 uint16_t NFA:1; /* Null Frame Indicator channel A */
3755 uint16_t SUA:1; /* Startup Frame Indicator channel A */
3756 uint16_t SEA:1; /* Syntax Error on channel A */
3757 uint16_t CEA:1; /* Content Error on channel A */
3758 uint16_t BVA:1; /* Boundary Violation on channel A */
3759 uint16_t:1;
3760 } RX;
3761 struct {
3762 uint16_t VFB:1; /* Valid Frame on channel B */
3763 uint16_t SYB:1; /* Sync Frame Indicator channel B */
3764 uint16_t NFB:1; /* Null Frame Indicator channel B */
3765 uint16_t SUB:1; /* Startup Frame Indicator channel B */
3766 uint16_t SEB:1; /* Syntax Error on channel B */
3767 uint16_t CEB:1; /* Content Error on channel B */
3768 uint16_t BVB:1; /* Boundary Violation on channel B */
3769 uint16_t TCB:1; /* Tx Conflict on channel B */
3770 uint16_t VFA:1; /* Valid Frame on channel A */
3771 uint16_t SYA:1; /* Sync Frame Indicator channel A */
3772 uint16_t NFA:1; /* Null Frame Indicator channel A */
3773 uint16_t SUA:1; /* Startup Frame Indicator channel A */
3774 uint16_t SEA:1; /* Syntax Error on channel A */
3775 uint16_t CEA:1; /* Content Error on channel A */
3776 uint16_t BVA:1; /* Boundary Violation on channel A */
3777 uint16_t TCA:1; /* Tx Conflict on channel A */
3778 } TX;
3779 uint16_t R;
3780 } S_STATUS_t;
3781
3782 typedef struct uMB_HEADER /* message buffer header */
3783 {
3784 F_HEADER_t FRAME_HEADER;
3785 uint16_t DATA_OFFSET;
3786 S_STATUS_t SLOT_STATUS;
3787 } MB_HEADER_t;
3788/****************************************************************************/
3789/* MODULE : MLB */
3790/****************************************************************************/
3791 struct MLB_tag {
3792
3793 union { /* MLB Module Configuration Register */
3794 uint32_t R;
3795 struct {
3796 uint32_t MDIS:1;
3797 uint32_t:15;
3798 uint32_t MDATOBSE:1;
3799 uint32_t MSIGOBS:1;
3800 uint32_t MSLOTE:1;
3801 uint32_t:2;
3802 uint32_t MSVRQIE:1;
3803 uint32_t MDATRQE:1;
3804 uint32_t:2;
3805 uint32_t MSVRQDL:3;
3806 uint32_t MSVRQCIE:1;
3807 uint32_t MIFSEL:1;
3808 uint32_t MSBFEPOL:1;
3809 uint32_t MDBFEPOL:1;
3810 } B;
3811 } MCR;
3812
3813 union { /* MLB Blank Register */
3814 uint32_t R;
3815 struct {
3816 uint32_t:31;
3817 uint32_t BLANK:1;
3818 } B;
3819 } MBR;
3820
3821 union { /* MLB Status Register */
3822 uint32_t R;
3823 struct {
3824 uint32_t:29;
3825 uint32_t MDATRQS:1;
3826 uint32_t MSYSS:1;
3827 uint32_t MSVRQS:1;
3828 } B;
3829 } MSR;
3830
3831 union { /* RX Control Channel Address Register */
3832 uint32_t R;
3833 struct {
3834 uint32_t RXCCHA_ACEN:1;
3835 uint32_t:25;
3836 uint32_t RXCCHA:5;
3837 uint32_t:1;
3838 } B;
3839 } RXCCHAR;
3840
3841 union { /* RX Async Channel Address Register */
3842 uint32_t R;
3843 struct {
3844 uint32_t RXACHA_ACEN:1;
3845 uint32_t:25;
3846 uint32_t RXACHA:5;
3847 uint32_t:1;
3848 } B;
3849 } RXACHAR;
3850
3851 union { /* TX Control Channel Address Register */
3852 uint32_t R;
3853 struct {
3854 uint32_t TXCCHA_ACEN:1;
3855 uint32_t:25;
3856 uint32_t TXCCHA:5;
3857 uint32_t:1;
3858 } B;
3859 } TXCCHAR;
3860
3861 union { /* TX Async Channel Address Register */
3862 uint32_t R;
3863 struct {
3864 uint32_t TXACHA_ACEN:1;
3865 uint32_t:25;
3866 uint32_t TXACHA:5;
3867 uint32_t:1;
3868 } B;
3869 } TXACHAR;
3870
3871 union { /* TX Sync Channel Address Register */
3872 uint32_t R;
3873 struct {
3874 uint32_t TXSCHA_ACEN:1;
3875 uint32_t:25;
3876 uint32_t TXSCHA:5;
3877 uint32_t:1;
3878 } B;
3879 } TXSCHAR;
3880
3881 union { /* TX Sync Channel Address Mask Register */
3882 uint32_t R;
3883 struct {
3884 uint32_t:26;
3885 uint32_t TXSCHAM:5;
3886 uint32_t:1;
3887 } B;
3888 } TXSCHAMR;
3889
3890 union { /* Clock Adjust Control Register */
3891 uint32_t R;
3892 struct {
3893 uint32_t:16;
3894 uint32_t PDLY:16;
3895 } B;
3896 } CLKACR;
3897
3898 union { /* RX Isochronous Channel Address Register */
3899 uint32_t R;
3900 struct {
3901 uint32_t RXICHA_ACEN:1;
3902 uint32_t:25;
3903 uint32_t RXICHA:5;
3904 uint32_t:1;
3905 } B;
3906 } RXICHAR;
3907
3908 union { /* TX Isochronous Channel Address Register */
3909 uint32_t R;
3910 struct {
3911 uint32_t TXICHA_ACEN:1;
3912 uint32_t:25;
3913 uint32_t TXICHA:5;
3914 uint32_t:1;
3915 } B;
3916 } TXICHAR;
3917
3918 };
3919
3920/* Define memories */
3921
3922#define SRAM_START 0x40000000UL
3923#define SRAM_SIZE 0x14000UL
3924#define SRAM_END 0x40013FFFUL
3925
3926#define FLASH_START 0x0UL
3927#define FLASH_SIZE 0x180000UL
3928#define FLASH_END 0x17FFFFUL
3929
3930/* Define instances of modules */
3931#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL)
3932#define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL)
3933#define MCM (*(volatile struct MCM_tag *) 0xFFF40000UL)
3934#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
3935#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
3936#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000UL)
3937#define MLB (*(volatile struct MLB_tag *) 0xFFF84000UL)
3938#define I2C (*(volatile struct I2C_tag *) 0xFFF88000UL)
3939#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL)
3940#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL)
3941#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000UL)
3942#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
3943#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL)
3944#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL)
3945#define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL)
3946#define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL)
3947#define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL)
3948#define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL)
3949#define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL)
3950#define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL)
3951#define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
3952#define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
3953#define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
3954#define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
3955#define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
3956#define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
3957#define FR (*(volatile struct FR_tag *) 0xFFFD8000UL)
3958#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
3959#define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL)
3960#define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL)
3961#define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL)
3962#define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL)
3963#define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL)
3964#define EBI (*(volatile struct EBI_tag *) 0xFFFF4000UL)
3965#define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL)
3966
3967#ifdef __MWERKS__
3968#pragma pop
3969#endif
3970
3971#ifdef __cplusplus
3972}
3973#endif
3974#endif /* ASM */
3975#endif /* ifdef _MPC5510_H */
3976/*********************************************************************
3977 *
3978 * Copyright:
3979 * Freescale Semiconductor, INC. All Rights Reserved.
3980 * You are hereby granted a copyright license to use, modify, and
3981 * distribute the SOFTWARE so long as this entire notice is
3982 * retained without alteration in any modified and/or redistributed
3983 * versions, and that such modified versions are clearly identified
3984 * as such. No licenses are granted by implication, estoppel or
3985 * otherwise under any patents or trademarks of Freescale
3986 * Semiconductor, Inc. This software is provided on an "AS IS"
3987 * basis and without warranty.
3988 *
3989 * To the maximum extent permitted by applicable law, Freescale
3990 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
3991 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
3992 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
3993 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
3994 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
3995 *
3996 * To the maximum extent permitted by applicable law, IN NO EVENT
3997 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
3998 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
3999 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
4000 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
4001 *
4002 * Freescale Semiconductor assumes no responsibility for the
4003 * maintenance and support of this software
4004 *
4005 ********************************************************************/
CRP_tag
Definition: fsl-mpc551x.h:73
DMAMUX_tag
Definition: fsl-mpc551x.h:230
DSPI_tag
Definition: fsl-mpc551x.h:244
EBI_CAL_CS_tag
Definition: fsl-mpc551x.h:479
EBI_CS_tag
Definition: fsl-mpc551x.h:447
EBI_tag
Definition: fsl-mpc551x.h:483
EMIOS_tag::EMIOS_CH_tag
Definition: fsl-mpc551x.h:642
EMIOS_tag
Definition: fsl-mpc551x.h:531
EQADC_tag
Definition: fsl-mpc551x.h:716
ESCI_tag
Definition: fsl-mpc551x.h:899
FLASH_tag
Definition: fsl-mpc551x.h:1027
FLEXCAN_tag::canbuf_t
Definition: fsl-mpc551x.h:1438
FLEXCAN_tag
Definition: fsl-mpc551x.h:1171
FMPLL_tag
Definition: fsl-mpc551x.h:1484
FR_tag
Definition: fsl-mpc551x.h:3622
I2C_tag
Definition: fsl-mpc551x.h:1539
INTC_tag
Definition: fsl-mpc551x.h:1603
MCM_tag
Definition: fsl-mpc551x.h:1692
MLB_tag
Definition: fsl-mpc551x.h:3791
MPU_tag
Definition: fsl-mpc551x.h:1843
PIT_tag
Definition: fsl-mpc551x.h:1991
SEMA4_tag
Definition: fsl-mpc551x.h:2087
SIU_tag
Definition: fsl-mpc551x.h:2221
uMB_HEADER
Definition: fsl-mpc551x.h:3783
uMSG_BUFF_CCS
Definition: fsl-mpc551x.h:3481
DSPI_tag::DSPI_CTAR_tag
Definition: fsl-mpc551x.h:284
DSPI_tag::DSPI_MCR_tag
Definition: fsl-mpc551x.h:245
DSPI_tag::DSPI_POPR_tag
Definition: fsl-mpc551x.h:362
DSPI_tag::DSPI_PUSHR_tag
Definition: fsl-mpc551x.h:344
DSPI_tag::DSPI_RSER_tag
Definition: fsl-mpc551x.h:325
DSPI_tag::DSPI_SR_tag
Definition: fsl-mpc551x.h:303
EBI_tag::EBI_MCR_tag
Definition: fsl-mpc551x.h:484
EMIOS_tag::EMIOS_CH_tag::EMIOS_CCR_tag
Definition: fsl-mpc551x.h:667
EMIOS_tag::EMIOS_CH_tag::EMIOS_CSR_tag
Definition: fsl-mpc551x.h:691
EMIOS_tag::EMIOS_MCR_tag
Definition: fsl-mpc551x.h:532
ESCI_tag::ESCI_CR1_tag
Definition: fsl-mpc551x.h:900
ESCI_tag::ESCI_CR2_tag
Definition: fsl-mpc551x.h:924
ESCI_tag::ESCI_DR_tag
Definition: fsl-mpc551x.h:946
ESCI_tag::ESCI_SR_tag
Definition: fsl-mpc551x.h:956
FLASH_tag::HLR_tag
Definition: fsl-mpc551x.h:1070
FLASH_tag::LMLR_tag
Definition: fsl-mpc551x.h:1057
FLASH_tag::SLMLR_tag
Definition: fsl-mpc551x.h:1079
FMPLL_tag::FMPLL_ESYNCR1_tag
Definition: fsl-mpc551x.h:1505
FMPLL_tag::FMPLL_ESYNCR2_tag
Definition: fsl-mpc551x.h:1517
FMPLL_tag::FMPLL_SYNSR_tag
Definition: fsl-mpc551x.h:1488
SIU_tag::SIU_DIRER_tag
Definition: fsl-mpc551x.h:2294
SIU_tag::SIU_DIRSR_tag
Definition: fsl-mpc551x.h:2317
SIU_tag::SIU_EISR_tag
Definition: fsl-mpc551x.h:2269
SIU_tag::SIU_IDFR_tag
Definition: fsl-mpc551x.h:2425
SIU_tag::SIU_IFEER_tag
Definition: fsl-mpc551x.h:2400
SIU_tag::SIU_IREER_tag
Definition: fsl-mpc551x.h:2375
SIU_tag::SIU_ORER_tag
Definition: fsl-mpc551x.h:2352
SIU_tag::SIU_PCR_tag
Definition: fsl-mpc551x.h:2460
uCASERCR
Definition: fsl-mpc551x.h:3540
uCBSERCR
Definition: fsl-mpc551x.h:3543
uCHIERFR
Definition: fsl-mpc551x.h:2939
uCIFRR
Definition: fsl-mpc551x.h:3037
uCYCTR
Definition: fsl-mpc551x.h:3546
uF_HEADER
Definition: fsl-mpc551x.h:3724
uGIFER
Definition: fsl-mpc551x.h:2842
uLDTXSLAR
Definition: fsl-mpc551x.h:3615
uLDTXSLBR
Definition: fsl-mpc551x.h:3618
uMBDSR
Definition: fsl-mpc551x.h:2807
uMBIVEC
Definition: fsl-mpc551x.h:2960
uMBSSUTR
Definition: fsl-mpc551x.h:2817
uMCR
Definition: fsl-mpc551x.h:2781
uMTCTR
Definition: fsl-mpc551x.h:3549
uMTSCFR
Definition: fsl-mpc551x.h:3171
uMVR
Definition: fsl-mpc551x.h:2773
uNMVLR
Definition: fsl-mpc551x.h:3576
uNMVR
Definition: fsl-mpc551x.h:3573
uOFCORVR
Definition: fsl-mpc551x.h:3561
uPADR
Definition: fsl-mpc551x.h:3534
uPCR0
Definition: fsl-mpc551x.h:3228
uPCR10
Definition: fsl-mpc551x.h:3313
uPCR11
Definition: fsl-mpc551x.h:3322
uPCR12
Definition: fsl-mpc551x.h:3331
uPCR13
Definition: fsl-mpc551x.h:3339
uPCR14
Definition: fsl-mpc551x.h:3347
uPCR15
Definition: fsl-mpc551x.h:3355
uPCR16
Definition: fsl-mpc551x.h:3362
uPCR17
Definition: fsl-mpc551x.h:3370
uPCR18
Definition: fsl-mpc551x.h:3377
uPCR19
Definition: fsl-mpc551x.h:3385
uPCR1
Definition: fsl-mpc551x.h:3236
uPCR20
Definition: fsl-mpc551x.h:3393
uPCR21
Definition: fsl-mpc551x.h:3401
uPCR22
Definition: fsl-mpc551x.h:3409
uPCR23
Definition: fsl-mpc551x.h:3418
uPCR24
Definition: fsl-mpc551x.h:3425
uPCR25
Definition: fsl-mpc551x.h:3434
uPCR26
Definition: fsl-mpc551x.h:3441
uPCR27
Definition: fsl-mpc551x.h:3450
uPCR28
Definition: fsl-mpc551x.h:3457
uPCR29
Definition: fsl-mpc551x.h:3465
uPCR2
Definition: fsl-mpc551x.h:3244
uPCR30
Definition: fsl-mpc551x.h:3473
uPCR3
Definition: fsl-mpc551x.h:3252
uPCR4
Definition: fsl-mpc551x.h:3261
uPCR5
Definition: fsl-mpc551x.h:3269
uPCR6
Definition: fsl-mpc551x.h:3278
uPCR7
Definition: fsl-mpc551x.h:3287
uPCR8
Definition: fsl-mpc551x.h:3295
uPCR9
Definition: fsl-mpc551x.h:3304
uPDAR
Definition: fsl-mpc551x.h:3537
uPIER0
Definition: fsl-mpc551x.h:2901
uPIER1
Definition: fsl-mpc551x.h:2922
uPIFR0
Definition: fsl-mpc551x.h:2863
uPIFR1
Definition: fsl-mpc551x.h:2884
uPOCR
Definition: fsl-mpc551x.h:2828
uPSR0
Definition: fsl-mpc551x.h:2971
uPSR1
Definition: fsl-mpc551x.h:2987
uPSR2
Definition: fsl-mpc551x.h:3000
uPSR3
Definition: fsl-mpc551x.h:3018
uRFARIR
Definition: fsl-mpc551x.h:3597
uRFBRIR
Definition: fsl-mpc551x.h:3600
uRFDSR
Definition: fsl-mpc551x.h:3193
uRFFIDRFMR
Definition: fsl-mpc551x.h:3612
uRFFIDRFVR
Definition: fsl-mpc551x.h:3609
uRFMIAFMR
Definition: fsl-mpc551x.h:3606
uRFMIDAFVR
Definition: fsl-mpc551x.h:3603
uRFRFCFR
Definition: fsl-mpc551x.h:3202
uRFRFCTR
Definition: fsl-mpc551x.h:3213
uRFSIR
Definition: fsl-mpc551x.h:3594
uRFSR
Definition: fsl-mpc551x.h:3591
uRSBIR
Definition: fsl-mpc551x.h:3182
uRTCORVR
Definition: fsl-mpc551x.h:3558
uSFCNTR
Definition: fsl-mpc551x.h:3059
uSFIDAFMR
Definition: fsl-mpc551x.h:3570
uSFIDAFVR
Definition: fsl-mpc551x.h:3567
uSFIDRFR
Definition: fsl-mpc551x.h:3085
uSFTCCSR
Definition: fsl-mpc551x.h:3069
uSFTOR
Definition: fsl-mpc551x.h:3564
uSLTCTAR
Definition: fsl-mpc551x.h:3552
uSLTCTBR
Definition: fsl-mpc551x.h:3555
uSSCCR
Definition: fsl-mpc551x.h:3134
uSSCR
Definition: fsl-mpc551x.h:3588
uSSR
Definition: fsl-mpc551x.h:3150
uSSSR
Definition: fsl-mpc551x.h:3123
uSTBSCR
Definition: fsl-mpc551x.h:2796
uSYMATOR
Definition: fsl-mpc551x.h:3051
uSYSBADHR
Definition: fsl-mpc551x.h:3528
uSYSBADLR
Definition: fsl-mpc551x.h:3531
uS_STSTUS
Definition: fsl-mpc551x.h:3742
uT1MTOR
Definition: fsl-mpc551x.h:3579
uTI1CYSR
Definition: fsl-mpc551x.h:3112
uTI2CR0
Definition: fsl-mpc551x.h:3582
uTI2CR1
Definition: fsl-mpc551x.h:3585
uTICCR
Definition: fsl-mpc551x.h:3093
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