RTEMS 5.2
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irq.h
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1
9/*
10 * Copyright (c) 2018 embedded brains GmbH
11 *
12 * Copyright (c) 2015 University of York.
13 * Hesham Almatary <hesham@alumni.york.ac.uk>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 */
36
37#ifndef LIBBSP_RISCV_GRISCV_IRQ_H
38#define LIBBSP_RISCV_GRISCV_IRQ_H
39
40#ifndef ASM
41
42#include <bsp.h>
43#include <rtems/irq.h>
44#include <rtems/irq-extension.h>
46
47#define RISCV_INTERRUPT_VECTOR_SOFTWARE 0
48
49#define RISCV_INTERRUPT_VECTOR_TIMER 1
50
51#define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2)
52
53#define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2)
54
55#define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2)
56
57#define BSP_INTERRUPT_VECTOR_MIN 0
58
59#define BSP_INTERRUPT_VECTOR_MAX RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1)
60
61void bsp_interrupt_set_affinity(
63 const Processor_mask *affinity
64);
65
66void bsp_interrupt_get_affinity(
68 Processor_mask *affinity
69);
70
71#endif /* ASM */
72
73#endif /* LIBBSP_RISCV_GRISCV_IRQ_H */
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
Header file for the Interrupt Manager Extension.
Processor Mask API.