23#ifndef LIBBSP_NIOS2_NIOS2_ISS_BSP_H
24#define LIBBSP_NIOS2_NIOS2_ISS_BSP_H
50#define SYSTEM_BUS_WIDTH 32
52#define JTAG_UART_BASE 0x08000000
53#define JTAG_UART_IRQ 2
55#define CLOCK_BASE 0x08001000
56#define CLOCK_FREQ 50000000
59#define TIMER_BASE 0x08002000
60#define TIMER_FREQ 50000000
65#define NIOS2_BYPASS_CACHE ((uint32_t)0x80000000ul)
66#define NIOS2_IO_BASE(x) ( (void*) ((uint32_t)x | NIOS2_BYPASS_CACHE ) )
67#define NIOS2_IENABLE(x) do{ __builtin_wrctl(3,__builtin_rdctl(3)|x);}while(0)
68#define NIOS2_IRQ_ENABLE(x) do {__builtin_wrctl(3,__builtin_rdctl(3)|x);} while(0)
73#ifndef SYSTEM_BUS_WIDTH
74#error SYSTEM_BUS_WIDTH is undefined
77#if SYSTEM_BUS_WIDTH != 32
78#error Only SYSTEM_BUS_WIDTH 32 is supported
83 volatile uint32_t status;
85 volatile uint32_t period_lo;
86 volatile uint32_t period_hi;
87 volatile uint32_t snap_lo;
88 volatile uint32_t snap_hi;
92#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1)
93#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0)
94#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2)
95#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1)
97#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1)
98#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0)
99#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2)
100#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1)
101#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4)
102#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2)
103#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8)
104#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3)
108 volatile uint32_t data;
113#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FFu)
114#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0)
115#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000u)
116#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15)
117#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000u)
118#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16)
120#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001u)
121#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0)
122#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002u)
123#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1)
124#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100u)
125#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8)
126#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200u)
127#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9)
128#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400u)
129#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10)
130#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000u)
131#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16)
138 rtems_isr_entry handler,
DEFAULT_INITIAL_EXTENSION Support.
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47
rtems_isr_entry set_vector(rtems_isr_entry handler, rtems_vector_number vector, int type)
Install an interrupt handler.
Definition: setvec.c:28
Definition: intercom.c:74