RTEMS 5.2
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irq.h
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1
9/*
10 * COPYRIGHT (c) 1989-2012.
11 * On-Line Applications Research Corporation (OAR).
12 *
13 * The license and distribution terms for this file may be
14 * found in the file LICENSE in this distribution or at
15 * http://www.rtems.org/license/LICENSE.
16 */
17
18#ifndef LIBBSP_MIPS_AU1X00_IRQ_H
19#define LIBBSP_MIPS_AU1X00_IRQ_H
20
21#ifndef ASM
22 #include <rtems.h>
23 #include <rtems/irq.h>
24 #include <rtems/irq-extension.h>
25 #include <rtems/score/mips.h>
26#endif
27
34/*
35 * Interrupt Vector Numbers
36 *
37 */
38/* MIPS_INTERRUPT_BASE should be 32 (0x20) */
39#define BSP_INTERRUPT_VECTOR_MIN 0
40#define AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0)
41#define AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1)
42#define AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2)
43#define AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3)
44#define AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4)
45#define AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5)
46#define AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6)
47#define AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7)
48
49#define AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8)
50#define AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8)
51#define AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9)
52#define AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10)
53#define AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11)
54#define AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12)
55#define AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13)
56#define AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14)
57#define AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15)
58#define AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16)
59#define AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17)
60#define AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18)
61#define AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19)
62#define AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20)
63#define AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21)
64#define AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22)
65#define AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23)
66#define AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24)
67#define AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25)
68#define AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26)
69#define AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27)
70#define AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28)
71#define AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29)
72#define AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30)
73#define AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31)
74#define AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32)
75#define AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33)
76#define AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34)
77#define AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35)
78#define AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36)
79#define AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37)
80#define AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38)
81#define AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39)
82
83#define AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40)
84#define AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40)
85#define AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41)
86#define AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42)
87#define AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43)
88#define AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44)
89#define AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45)
90#define AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46)
91#define AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47)
92#define AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48)
93#define AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49)
94#define AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50)
95#define AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51)
96#define AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52)
97#define AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53)
98#define AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54)
99#define AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55)
100#define AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56)
101#define AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57)
102#define AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58)
103#define AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59)
104#define AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60)
105#define AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61)
106#define AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62)
107#define AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63)
108#define AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64)
109#define AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65)
110#define AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66)
111#define AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67)
112#define AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68)
113#define AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69)
114#define AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70)
115#define AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71)
116
117#define AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72)
118
119#define BSP_INTERRUPT_VECTOR_MAX AU1X00_MAXIMUM_VECTORS
120
123#endif /* LIBBSP_MIPS_AU1X00_IRQ_H */
Header file for the Interrupt Manager Extension.
Information to build RTEMS for a "no cpu" while in protected mode.