15#ifndef RTEMS_SCORE_ARMV4_H
16#define RTEMS_SCORE_ARMV4_H
18#include <rtems/score/cpu.h>
24#ifdef ARM_MULTILIB_ARCH_V4
28void _ARMV4_Exception_interrupt(
void );
32void _ARMV4_Exception_data_abort_set_handler(
33 ARMV4_Exception_abort_handler handler
36void _ARMV4_Exception_data_abort(
void );
38void _ARMV4_Exception_prefetch_abort_set_handler(
39 ARMV4_Exception_abort_handler handler
42void _ARMV4_Exception_prefetch_abort(
void );
44void _ARMV4_Exception_undef_default(
void );
46void _ARMV4_Exception_swi_default(
void );
48void _ARMV4_Exception_data_abort_default(
void );
50void _ARMV4_Exception_pref_abort_default(
void );
52void _ARMV4_Exception_reserved_default(
void );
54void _ARMV4_Exception_irq_default(
void );
56void _ARMV4_Exception_fiq_default(
void );
58static inline uint32_t _ARMV4_Status_irq_enable(
void )
60 uint32_t arm_switch_reg;
68 "bic %[arm_switch_reg], %[psr], #0x80\n"
69 "msr cpsr, %[arm_switch_reg]\n"
71 : [arm_switch_reg]
"=&r" (arm_switch_reg), [psr]
"=&r" (psr)
77static inline void _ARMV4_Status_restore( uint32_t psr )
void bsp_interrupt_dispatch(void)
Interrupt dispatch.
Definition: irq.c:83
#define RTEMS_COMPILER_MEMORY_BARRIER()
Definition: basedefs.h:77
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
The set of registers that specifies the complete processor state.
Definition: cpu.h:629