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cpu.h
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1 
10 /*
11  * COPYRIGHT (c) 1989-2008.
12  * On-Line Applications Research Corporation (OAR).
13  *
14  * The license and distribution terms for this file may be
15  * found in the file LICENSE in this distribution or at
16  * http://www.rtems.org/license/LICENSE.
17  */
18 
19 #ifndef _RTEMS_SCORE_CPU_H
20 #define _RTEMS_SCORE_CPU_H
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 #include <rtems/score/basedefs.h>
27 #include <rtems/score/lm32.h>
28 
29 /* conditional compilation parameters */
30 
42 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
43 
53 #define CPU_ISR_PASSES_FRAME_POINTER TRUE
54 
55 #define CPU_HARDWARE_FP FALSE
56 
57 #define CPU_SOFTWARE_FP FALSE
58 
83 #define CPU_ALL_TASKS_ARE_FP FALSE
84 
100 #define CPU_IDLE_TASK_IS_FP FALSE
101 
131 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
132 
133 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
134 
146 #define CPU_STACK_GROWS_UP FALSE
147 
148 /* L2 cache lines are 32 bytes in Milkymist SoC */
149 #define CPU_CACHE_LINE_BYTES 32
150 
151 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
152 
163 #define CPU_MODES_INTERRUPT_MASK 0x00000001
164 
165 #define CPU_MAXIMUM_PROCESSORS 32
166 
167 /*
168  * Processor defined structures required for cpukit/score.
169  *
170  * Port Specific Information:
171  *
172  * XXX document implementation including references if appropriate
173  */
174 
175 /* may need to put some structures here. */
176 
227 typedef struct {
228  uint32_t r11;
229  uint32_t r12;
230  uint32_t r13;
231  uint32_t r14;
232  uint32_t r15;
233  uint32_t r16;
234  uint32_t r17;
235  uint32_t r18;
236  uint32_t r19;
237  uint32_t r20;
238  uint32_t r21;
239  uint32_t r22;
240  uint32_t r23;
241  uint32_t r24;
242  uint32_t r25;
243  uint32_t gp;
244  uint32_t fp;
245  uint32_t sp;
246  uint32_t ra;
247  uint32_t ie;
248  uint32_t epc;
250 
259 #define _CPU_Context_Get_SP( _context ) \
260  (_context)->sp
261 
267 typedef struct {
268  uint32_t r1;
269  uint32_t r2;
270  uint32_t r3;
271  uint32_t r4;
272  uint32_t r5;
273  uint32_t r6;
274  uint32_t r7;
275  uint32_t r8;
276  uint32_t r9;
277  uint32_t r10;
278  uint32_t ra;
279  uint32_t ba;
280  uint32_t ea;
282 
293 #if 0
295 #endif
296 
307 /*
308  * Nothing prevents the porter from declaring more CPU specific variables.
309  *
310  * Port Specific Information:
311  *
312  * XXX document implementation including references if appropriate
313  */
314 
315 /* XXX: if needed, put more variables here */
316 
327 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
328 
338 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
339 
344 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
345 
351 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
352 
353 
363 #define CPU_STACK_MINIMUM_SIZE (1024*4)
364 
365 #define CPU_SIZEOF_POINTER 4
366 
377 #define CPU_ALIGNMENT 4
378 
402 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
403 
414 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
415 
416 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
417 
418 /*
419  * ISR handler macros
420  */
421 
434 #define _CPU_Initialize_vectors()
435 
446 #define _CPU_ISR_Disable( _isr_cookie ) \
447  lm32_disable_interrupts( _isr_cookie );
448 
460 #define _CPU_ISR_Enable( _isr_cookie ) \
461  lm32_enable_interrupts( _isr_cookie );
462 
475 #define _CPU_ISR_Flash( _isr_cookie ) \
476  lm32_flash_interrupts( _isr_cookie );
477 
478 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
479 {
480  return ( level & 0x0001 ) != 0;
481 }
482 
498 #define _CPU_ISR_Set_level( new_level ) \
499  { \
500  _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
501  }
502 
513 uint32_t _CPU_ISR_Get_level( void );
514 
515 /* end of ISR handler macros */
516 
519 /* Context handler macros */
520 
552 extern char _gp[];
553 
554 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
555  _isr, _entry_point, _is_fp, _tls_area ) \
556  do { \
557  uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
558  \
559  (void) _is_fp; /* avoid warning for being unused */ \
560  (void) _isr; /* avoid warning for being unused */ \
561  (_the_context)->gp = (uint32_t)_gp; \
562  (_the_context)->fp = (uint32_t)_stack; \
563  (_the_context)->sp = (uint32_t)_stack; \
564  (_the_context)->ra = (uint32_t)(_entry_point); \
565  } while ( 0 )
566 
582 #define _CPU_Context_Restart_self( _the_context ) \
583  _CPU_Context_restore( (_the_context) );
584 
603 #define _CPU_Context_Initialize_fp( _destination )
604 #if 0
605  { \
606  *(*(_destination)) = _CPU_Null_fp_context; \
607  }
608 #endif
609 
610 /* end of Context handler macros */
611 
612 /* Fatal Error manager macros */
613 
623 #define _CPU_Fatal_halt( _source, _error ) \
624  { \
625  }
626 
627 /* end of Fatal Error manager macros */
628 
629 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
630 
631 /* functions */
632 
640 void _CPU_Initialize(void);
641 
647 typedef void ( *CPU_ISR_raw_handler )( void );
648 
650  uint32_t vector,
651  CPU_ISR_raw_handler new_handler,
652  CPU_ISR_raw_handler *old_handler
653 )
654 {
655  /* TODO */
656 }
657 
658 typedef void ( *CPU_ISR_handler )( uint32_t );
659 
661  uint32_t vector,
662  CPU_ISR_handler new_handler,
663  CPU_ISR_handler *old_handler
664 );
665 
668 void *_CPU_Thread_Idle_body( uintptr_t ignored );
669 
682  Context_Control *run,
683  Context_Control *heir
684 );
685 
704  Context_Control *new_context
706 
709 /* FIXME */
711 
713 
750 static inline uint32_t CPU_swap_u32(
751  uint32_t value
752 )
753 {
754  uint32_t byte1, byte2, byte3, byte4, swapped;
755 
756  byte4 = (value >> 24) & 0xff;
757  byte3 = (value >> 16) & 0xff;
758  byte2 = (value >> 8) & 0xff;
759  byte1 = value & 0xff;
760 
761  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
762  return swapped;
763 }
764 
771 static inline uint16_t CPU_swap_u16(uint16_t v)
772 {
773  return v << 8 | v >> 8;
774 }
775 
778 typedef uint32_t CPU_Counter_ticks;
779 
780 uint32_t _CPU_Counter_frequency( void );
781 
782 CPU_Counter_ticks _CPU_Counter_read( void );
783 
784 static inline CPU_Counter_ticks _CPU_Counter_difference(
785  CPU_Counter_ticks second,
786  CPU_Counter_ticks first
787 )
788 {
789  return second - first;
790 }
791 
793 typedef uintptr_t CPU_Uint32ptr;
794 
795 #ifdef __cplusplus
796 }
797 #endif
798 
799 #endif
#define sp
stack-pointer */
Definition: regs.h:64
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:194
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
unsigned ie
Definition: tte.h:76
LM32 Set up Basic CPU Dependency Settings Based on Compiler Settings.
Interrupt stack frame (ISF).
Definition: cpu.h:191
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
#define fp
frame-pointer */
Definition: regs.h:65
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
#define CPU_swap_u16(value)
Definition: cpu.h:642
SPARC basic context.
Definition: cpu.h:194
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1210
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.h:649
Context_Control_fp _CPU_Null_fp_context
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.
Definition: cpu.h:375
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
Basic Definitions.
#define ra
return address */
Definition: regs.h:66
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:493
unsigned v
Definition: tte.h:73
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
#define gp
global data pointer */
Definition: regs.h:63