![]()  | 
  
    RTEMS
    5.1
    
   | 
 
Type definitions and defines for Cortex-M processor based devices. More...
Modules | |
| Core Debug Registers (CoreDebug) | |
| Type definitions for the Core Debug Registers.  | |
| Core Definitions | |
| Definitions for base addresses, unions, and structures.  | |
| Core register bit field macros | |
| Macros for use with bit field definitions (xxx_Pos, xxx_Msk).  | |
| Data Watchpoint and Trace (DWT) | |
| Type definitions for the Data Watchpoint and Trace (DWT)  | |
| Instrumentation Trace Macrocell (ITM) | |
| Type definitions for the Instrumentation Trace Macrocell (ITM)  | |
| Nested Vectored Interrupt Controller (NVIC) | |
| Type definitions for the NVIC Registers.  | |
| Status and Control Registers | |
| Core Register type definitions.  | |
| System Control Block (SCB) | |
| Type definitions for the System Control Block Registers.  | |
| System Controls not in SCB (SCnSCB) | |
| Type definitions for the System Control and ID Register not in the SCB.  | |
| System Tick Timer (SysTick) | |
| Type definitions for the System Timer Registers.  | |
| Trace Port Interface (TPI) | |
| Type definitions for the Trace Port Interface (TPI)  | |
Type definitions and defines for Cortex-M processor based devices.
 1.8.15