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#define  | ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT   1 | 
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#define  | ALT_QSPI_PAGE_ADDR_MSK   0xFFFFFF00 | 
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#define  | ALT_QSPI_PAGE_SIZE   0x00000100 | 
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#define  | ALT_QSPI_SUBSECTOR_ADDR_MSK   0xFFFFF000 | 
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#define  | ALT_QSPI_SUBSECTOR_SIZE   0x00001000 | 
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#define  | ALT_QSPI_SECTOR_ADDR_MSK   0xFFFF0000 | 
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#define  | ALT_QSPI_SECTOR_SIZE   0x00010000 | 
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#define  | ALT_QSPI_BANK_ADDR_MSK   0xFF000000 | 
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#define  | ALT_QSPI_BANK_SIZE   0x01000000 | 
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#define  | ALT_QSPI_N25Q_DIE_ADDR_MSK   0xFE000000 | 
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#define  | ALT_QSPI_N25Q_DIE_SIZE   0x02000000 | 
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#define  | ALT_QSPI_TSHSL_NS_DEF   (50) | 
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#define  | ALT_QSPI_TSD2D_NS_DEF   (0) | 
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#define  | ALT_QSPI_TCHSH_NS_DEF   (4) | 
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#define  | ALT_QSPI_TSLCH_NS_DEF   (4) | 
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#define  | ALT_QSPI_STIG_OPCODE_READ   (0x03) | 
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#define  | ALT_QSPI_STIG_OPCODE_4BYTE_READ   (0x13) | 
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#define  | ALT_QSPI_STIG_OPCODE_FASTREAD   (0x0B) | 
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#define  | ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT   (0x3B) | 
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#define  | ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT   (0x6B) | 
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#define  | ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO   (0xBB) | 
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#define  | ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO   (0xEB) | 
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#define  | ALT_QSPI_STIG_OPCODE_PP   (0x02) | 
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#define  | ALT_QSPI_STIG_OPCODE_DUAL_PP   (0xA2) | 
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#define  | ALT_QSPI_STIG_OPCODE_QUAD_PP   (0x32) | 
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#define  | ALT_QSPI_STIG_OPCODE_RDID   (0x9F) | 
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#define  | ALT_QSPI_STIG_OPCODE_WREN   (0x06) | 
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#define  | ALT_QSPI_STIG_OPCODE_WRDIS   (0x04) | 
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#define  | ALT_QSPI_STIG_OPCODE_RDSR   (0x05) | 
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#define  | ALT_QSPI_STIG_OPCODE_WRSR   (0x01) | 
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#define  | ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE   (0x20) | 
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#define  | ALT_QSPI_STIG_OPCODE_SEC_ERASE   (0xD8) | 
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#define  | ALT_QSPI_STIG_OPCODE_BULK_ERASE   (0xC7) | 
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#define  | ALT_QSPI_STIG_OPCODE_DIE_ERASE   (0xC4) | 
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#define  | ALT_QSPI_STIG_OPCODE_CHIP_ERASE   (0x60) | 
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#define  | ALT_QSPI_STIG_OPCODE_RD_EXT_REG   (0xC8) | 
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#define  | ALT_QSPI_STIG_OPCODE_WR_EXT_REG   (0xC5) | 
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#define  | ALT_QSPI_STIG_OPCODE_RD_STAT_REG   (0x05) | 
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#define  | ALT_QSPI_STIG_OPCODE_WR_STAT_REG   (0x01) | 
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#define  | ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE   (0xB7) | 
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#define  | ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE   (0xE9) | 
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#define  | ALT_QSPI_STIG_OPCODE_RESET_EN   (0x66) | 
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#define  | ALT_QSPI_STIG_OPCODE_RESET_MEM   (0x99) | 
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#define  | ALT_QSPI_STIG_OPCODE_RDFLGSR   (0x70) | 
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#define  | ALT_QSPI_STIG_OPCODE_CLRFLGSR   (0x50) | 
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#define  | ALT_QSPI_STIG_OPCODE_DISCVR_PARAM   (0x5A) | 
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#define  | QSPI_READ_CLK_MHZ   (50) | 
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#define  | QSPI_FASTREAD_CLK_MHZ   (100) | 
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#define  | ALT_QSPI_STIG_RDID_JEDECID_MICRON   (0x20) | 
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#define  | ALT_QSPI_STIG_RDID_JEDECID_NUMONYX   (0x20) | 
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#define  | ALT_QSPI_STIG_RDID_JEDECID_SPANSION   (0xEF) | 
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#define  | ALT_QSPI_STIG_RDID_JEDECID_WINBOND   (0xEF) | 
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#define  | ALT_QSPI_STIG_RDID_JEDECID_MACRONIC   (0xC2) | 
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#define  | ALT_QSPI_STIG_RDID_JEDECID_ATMEL   (0x1F) | 
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#define  | ALT_QSPI_STIG_RDID_JEDECID_GET(value)   ((value >>  0) & 0xff) | 
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#define  | ALT_QSPI_STIG_RDID_CAPACITYID_GET(value)   ((value >> 16) & 0xff) | 
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#define  | ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value)   ((value >> 7) & 0x1) | 
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#define  | ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value)   ((value >> 7) & 0x1) | 
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#define  | ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value)   ((value >> 7) & 0x1) | 
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#define  | ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value)   ((value >> 5) & 0x1) | 
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#define  | ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value)   ((value >> 4) & 0x1) | 
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#define  | ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value)   ((value >> 1) & 0x1) | 
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#define  | ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value)   ((value >> 0) & 0x1) | 
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#define  | ALT_QSPI_STIG_SR_BUSY_GET(value)   ((value >> 0) & 0x1) | 
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#define  | ALT_QSPI_TIMEOUT_INFINITE   (0xffffffff) | 
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ALT_STATUS_CODE  | alt_qspi_replace (uint32_t dst, const void *src, size_t size) | 
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ALT_STATUS_CODE  | alt_qspi_stig_cmd (uint32_t opcode, uint32_t dummy, uint32_t timeout) | 
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ALT_STATUS_CODE  | alt_qspi_stig_rd_cmd (uint8_t opcode, uint32_t dummy, uint32_t num_bytes, uint32_t *output, uint32_t timeout) | 
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ALT_STATUS_CODE  | alt_qspi_stig_wr_cmd (uint8_t opcode, uint32_t dummy, uint32_t num_bytes, const uint32_t *input, uint32_t timeout) | 
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ALT_STATUS_CODE  | alt_qspi_stig_addr_cmd (uint8_t opcode, uint32_t dummy, uint32_t address, uint32_t timeout) | 
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ALT_STATUS_CODE  | alt_qspi_device_wren (void) | 
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ALT_STATUS_CODE  | alt_qspi_device_wrdis (void) | 
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ALT_STATUS_CODE  | alt_qspi_device_rdid (uint32_t *rdid) | 
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ALT_STATUS_CODE  | alt_qspi_discovery_parameter (uint32_t *param) | 
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ALT_STATUS_CODE  | alt_qspi_device_bank_select (uint32_t bank) | 
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Altera - QSPI Flash Controller Module