27 #ifndef _RTEMS_SCORE_CPU_H 28 #define _RTEMS_SCORE_CPU_H 34 #include <rtems/score/types.h> 56 #define CPU_INLINE_ENABLE_DISPATCH FALSE 69 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 95 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE 96 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE 101 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE 109 #define CPU_ISR_PASSES_FRAME_POINTER 0 127 #define CPU_HARDWARE_FP TRUE 128 #define CPU_SOFTWARE_FP FALSE 130 #define CPU_SOFTWARE_FP FALSE 131 #define CPU_HARDWARE_FP FALSE 144 #define CPU_ALL_TASKS_ARE_FP TRUE 146 #define CPU_ALL_TASKS_ARE_FP FALSE 162 #define CPU_IDLE_TASK_IS_FP TRUE 164 #define CPU_IDLE_TASK_IS_FP FALSE 194 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 196 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 220 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE 230 #define CPU_STACK_GROWS_UP FALSE 252 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16))) 254 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE 264 #if defined(__LITTLE_ENDIAN__) 265 #define CPU_BIG_ENDIAN FALSE 266 #define CPU_LITTLE_ENDIAN TRUE 268 #define CPU_BIG_ENDIAN TRUE 269 #define CPU_LITTLE_ENDIAN FALSE 278 #define CPU_MODES_INTERRUPT_MASK 0x0000000f 280 #define CPU_PER_CPU_CONTROL_SIZE 0 358 #define _CPU_Context_Get_SP( _context ) \ 363 #ifdef SH4_USE_X_REGISTERS 379 } CPU_Interrupt_frame;
406 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 414 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 421 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 422 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 429 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 439 #define CPU_STACK_MINIMUM_SIZE 4096 441 #define CPU_SIZEOF_POINTER 4 449 #define CPU_ALIGNMENT 8 451 #define CPU_ALIGNMENT 4 466 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 480 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT 491 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT 503 #define _CPU_Initialize_vectors() 510 #define _CPU_ISR_Disable( _level) \ 511 sh_disable_interrupts( _level ) 519 #define _CPU_ISR_Enable( _level) \ 520 sh_enable_interrupts( _level) 529 #define _CPU_ISR_Flash( _level) \ 530 sh_flash_interrupts( _level) 543 #define _CPU_ISR_Set_level( _newlevel) \ 544 sh_set_interrupt_level(_newlevel) 581 void (*_entry_point)(
void),
595 #define _CPU_Context_Restart_self( _the_context ) \ 596 _CPU_Context_restore( (_the_context) ); 612 #define _CPU_Context_Fp_start( _base, _offset ) \ 613 ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) 629 #define _CPU_Context_Initialize_fp( _destination ) \ 631 *(*(_destination)) = _CPU_Null_fp_context;\ 634 #define _CPU_Context_Initialize_fp( _destination ) \ 651 #ifdef BSP_FATAL_HALT 653 void bsp_fatal_halt( uint32_t _error);
654 #define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error) 656 #define _CPU_Fatal_halt( _source, _error)\ 658 __asm__ volatile("mov.l %0,r0"::"m" (_error)); \ 659 __asm__ volatile("mov #1, r4"); \ 660 __asm__ volatile("trapa #34"); \ 723 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 724 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE 726 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 728 extern uint8_t _bit_set_table[];
730 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 733 if(_value > 0x00ff) \ 734 { _value >>= 8; _output = 8; } \ 735 if(_value > 0x000f) \ 736 { _output += 4; _value >>= 4; } \ 737 _output += _bit_set_table[ _value]; } 749 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 751 #define _CPU_Priority_Mask( _bit_number ) \ 752 ( 1 << (_bit_number) ) 763 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 765 #define _CPU_Priority_bits_index( _priority ) \ 894 CPU_Counter_ticks second,
895 CPU_Counter_ticks first
898 return second - first;
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: m68k/cpu.c:167
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: avr/cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: avr/cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: no_cpu/cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: no_cpu/cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: score/cpu/arm/rtems/score/cpu.h:248
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: m68k/cpu.c:176
void _CPU_Initialize(void)
CPU initialization.
Definition: avr/cpu.c:26
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: score/cpu/no_cpu/rtems/score/cpu.h:1461
Hitachi SH CPU Department Source.
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: avr/cpu.c:101
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: epiphany/cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: score/cpu/mips/rtems/score/cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: score/cpu/arm/rtems/score/cpu.h:294
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor's vector table...
Definition: avr/cpu.c:57
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: avr/cpu.c:125
The set of registers that specifies the complete processor state.
Definition: score/cpu/arm/rtems/score/cpu.h:671
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329