RTEMS CPU Kit with SuperCore
4.11.3
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chrisj
rtems
releases
rtems-release.git
4.11.3
ws-rtems
rtems-4.11.3
cpukit
score
cpu
avr
avr
iom161.h
Go to the documentation of this file.
1
9
/*
10
* Copyright (c) 2002, Marek Michalkiewicz
11
* All rights reserved.
12
*
13
* Redistribution and use in source and binary forms, with or without
14
* modification, are permitted provided that the following conditions are met:
15
*
16
* * Redistributions of source code must retain the above copyright
17
* notice, this list of conditions and the following disclaimer.
18
*
19
* * Redistributions in binary form must reproduce the above copyright
20
* notice, this list of conditions and the following disclaimer in
21
* the documentation and/or other materials provided with the
22
* distribution.
23
*
24
* * Neither the name of the copyright holders nor the names of
25
* contributors may be used to endorse or promote products derived
26
* from this software without specific prior written permission.
27
*
28
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38
* POSSIBILITY OF SUCH DAMAGE.
39
*/
40
41
#ifndef _AVR_IOM161_H_
42
#define _AVR_IOM161_H_ 1
43
51
#ifndef _AVR_IO_H_
52
# error "Include <avr/io.h> instead of this file."
53
#endif
54
55
#ifndef _AVR_IOXXX_H_
56
# define _AVR_IOXXX_H_ "iom161.h"
57
#else
58
# error "Attempt to include more than one <avr/ioXXX.h> file."
59
#endif
60
61
/* I/O registers */
62
63
/* UART1 Baud Rate Register */
64
#define UBRR1 _SFR_IO8(0x00)
65
66
/* UART1 Control and Status Registers */
67
#define UCSR1B _SFR_IO8(0x01)
68
#define UCSR1A _SFR_IO8(0x02)
69
70
/* UART1 I/O Data Register */
71
#define UDR1 _SFR_IO8(0x03)
72
73
/* 0x04 reserved */
74
75
/* Input Pins, Port E */
76
#define PINE _SFR_IO8(0x05)
77
78
/* Data Direction Register, Port E */
79
#define DDRE _SFR_IO8(0x06)
80
81
/* Data Register, Port E */
82
#define PORTE _SFR_IO8(0x07)
83
84
/* Analog Comparator Control and Status Register */
85
#define ACSR _SFR_IO8(0x08)
86
87
/* UART0 Baud Rate Register */
88
#define UBRR0 _SFR_IO8(0x09)
89
90
/* UART0 Control and Status Registers */
91
#define UCSR0B _SFR_IO8(0x0A)
92
#define UCSR0A _SFR_IO8(0x0B)
93
94
/* UART0 I/O Data Register */
95
#define UDR0 _SFR_IO8(0x0C)
96
97
/* SPI Control Register */
98
#define SPCR _SFR_IO8(0x0D)
99
100
/* SPI Status Register */
101
#define SPSR _SFR_IO8(0x0E)
102
103
/* SPI I/O Data Register */
104
#define SPDR _SFR_IO8(0x0F)
105
106
/* Input Pins, Port D */
107
#define PIND _SFR_IO8(0x10)
108
109
/* Data Direction Register, Port D */
110
#define DDRD _SFR_IO8(0x11)
111
112
/* Data Register, Port D */
113
#define PORTD _SFR_IO8(0x12)
114
115
/* Input Pins, Port C */
116
#define PINC _SFR_IO8(0x13)
117
118
/* Data Direction Register, Port C */
119
#define DDRC _SFR_IO8(0x14)
120
121
/* Data Register, Port C */
122
#define PORTC _SFR_IO8(0x15)
123
124
/* Input Pins, Port B */
125
#define PINB _SFR_IO8(0x16)
126
127
/* Data Direction Register, Port B */
128
#define DDRB _SFR_IO8(0x17)
129
130
/* Data Register, Port B */
131
#define PORTB _SFR_IO8(0x18)
132
133
/* Input Pins, Port A */
134
#define PINA _SFR_IO8(0x19)
135
136
/* Data Direction Register, Port A */
137
#define DDRA _SFR_IO8(0x1A)
138
139
/* Data Register, Port A */
140
#define PORTA _SFR_IO8(0x1B)
141
142
/* EEPROM Control Register */
143
#define EECR _SFR_IO8(0x1C)
144
145
/* EEPROM Data Register */
146
#define EEDR _SFR_IO8(0x1D)
147
148
/* EEPROM Address Register */
149
#define EEAR _SFR_IO16(0x1E)
150
#define EEARL _SFR_IO8(0x1E)
151
#define EEARH _SFR_IO8(0x1F)
152
153
/* UART Baud Register HIgh */
154
#define UBRRH _SFR_IO8(0x20)
155
156
/* Watchdog Timer Control Register */
157
#define WDTCR _SFR_IO8(0x21)
158
159
/* Timer/Counter2 Output Compare Register */
160
#define OCR2 _SFR_IO8(0x22)
161
162
/* Timer/Counter2 (8-bit) */
163
#define TCNT2 _SFR_IO8(0x23)
164
165
/* Timer/Counter1 Input Capture Register */
166
#define ICR1 _SFR_IO16(0x24)
167
#define ICR1L _SFR_IO8(0x24)
168
#define ICR1H _SFR_IO8(0x25)
169
170
/* ASynchronous mode Status Register */
171
#define ASSR _SFR_IO8(0x26)
172
173
/* Timer/Counter2 Control Register */
174
#define TCCR2 _SFR_IO8(0x27)
175
176
/* Timer/Counter1 Output Compare RegisterB */
177
#define OCR1B _SFR_IO16(0x28)
178
#define OCR1BL _SFR_IO8(0x28)
179
#define OCR1BH _SFR_IO8(0x29)
180
181
/* Timer/Counter1 Output Compare RegisterA */
182
#define OCR1A _SFR_IO16(0x2A)
183
#define OCR1AL _SFR_IO8(0x2A)
184
#define OCR1AH _SFR_IO8(0x2B)
185
186
/* Timer/Counter1 */
187
#define TCNT1 _SFR_IO16(0x2C)
188
#define TCNT1L _SFR_IO8(0x2C)
189
#define TCNT1H _SFR_IO8(0x2D)
190
191
/* Timer/Counter1 Control Register B */
192
#define TCCR1B _SFR_IO8(0x2E)
193
194
/* Timer/Counter1 Control Register A */
195
#define TCCR1A _SFR_IO8(0x2F)
196
197
/* Special Function IO Register */
198
#define SFIOR _SFR_IO8(0x30)
199
200
/* Timer/Counter0 Output Compare Register */
201
#define OCR0 _SFR_IO8(0x31)
202
203
/* Timer/Counter0 (8-bit) */
204
#define TCNT0 _SFR_IO8(0x32)
205
206
/* Timer/Counter0 Control Register */
207
#define TCCR0 _SFR_IO8(0x33)
208
209
/* MCU general Status Register */
210
#define MCUSR _SFR_IO8(0x34)
211
212
/* MCU general Control Register */
213
#define MCUCR _SFR_IO8(0x35)
214
215
/* Extended MCU general Control Register */
216
#define EMCUCR _SFR_IO8(0x36)
217
218
/* Store Program Memory Control Register */
219
#define SPMCR _SFR_IO8(0x37)
220
221
/* Timer/Counter Interrupt Flag Register */
222
#define TIFR _SFR_IO8(0x38)
223
224
/* Timer/Counter Interrupt MaSK Register */
225
#define TIMSK _SFR_IO8(0x39)
226
227
/* General Interrupt Flag Register */
228
#define GIFR _SFR_IO8(0x3A)
229
230
/* General Interrupt MaSK register */
231
#define GIMSK _SFR_IO8(0x3B)
232
233
/* 0x3C reserved */
234
235
/* 0x3D..0x3E SP */
236
237
/* 0x3F SREG */
238
239
/* Interrupt vectors */
240
241
/* External Interrupt 0 */
242
#define INT0_vect _VECTOR(1)
243
#define SIG_INTERRUPT0 _VECTOR(1)
244
245
/* External Interrupt 1 */
246
#define INT1_vect _VECTOR(2)
247
#define SIG_INTERRUPT1 _VECTOR(2)
248
249
/* External Interrupt 2 */
250
#define INT2_vect _VECTOR(3)
251
#define SIG_INTERRUPT2 _VECTOR(3)
252
253
/* Timer/Counter2 Compare Match */
254
#define TIMER2_COMP_vect _VECTOR(4)
255
#define SIG_OUTPUT_COMPARE2 _VECTOR(4)
256
257
/* Timer/Counter2 Overflow */
258
#define TIMER2_OVF_vect _VECTOR(5)
259
#define SIG_OVERFLOW2 _VECTOR(5)
260
261
/* Timer/Counter1 Capture Event */
262
#define TIMER1_CAPT_vect _VECTOR(6)
263
#define SIG_INPUT_CAPTURE1 _VECTOR(6)
264
265
/* Timer/Counter1 Compare Match A */
266
#define TIMER1_COMPA_vect _VECTOR(7)
267
#define SIG_OUTPUT_COMPARE1A _VECTOR(7)
268
269
/* Timer/Counter1 Compare Match B */
270
#define TIMER1_COMPB_vect _VECTOR(8)
271
#define SIG_OUTPUT_COMPARE1B _VECTOR(8)
272
273
/* Timer/Counter1 Overflow */
274
#define TIMER1_OVF_vect _VECTOR(9)
275
#define SIG_OVERFLOW1 _VECTOR(9)
276
277
/* Timer/Counter0 Compare Match */
278
#define TIMER0_COMP_vect _VECTOR(10)
279
#define SIG_OUTPUT_COMPARE0 _VECTOR(10)
280
281
/* Timer/Counter0 Overflow */
282
#define TIMER0_OVF_vect _VECTOR(11)
283
#define SIG_OVERFLOW0 _VECTOR(11)
284
285
/* Serial Transfer Complete */
286
#define SPI_STC_vect _VECTOR(12)
287
#define SIG_SPI _VECTOR(12)
288
289
/* UART0, Rx Complete */
290
#define UART0_RX_vect _VECTOR(13)
291
#define SIG_UART0_RECV _VECTOR(13)
292
293
/* UART1, Rx Complete */
294
#define UART1_RX_vect _VECTOR(14)
295
#define SIG_UART1_RECV _VECTOR(14)
296
297
/* UART0 Data Register Empty */
298
#define UART0_UDRE_vect _VECTOR(15)
299
#define SIG_UART0_DATA _VECTOR(15)
300
301
/* UART1 Data Register Empty */
302
#define UART1_UDRE_vect _VECTOR(16)
303
#define SIG_UART1_DATA _VECTOR(16)
304
305
/* UART0, Tx Complete */
306
#define UART0_TX_vect _VECTOR(17)
307
#define SIG_UART0_TRANS _VECTOR(17)
308
309
/* UART1, Tx Complete */
310
#define UART1_TX_vect _VECTOR(18)
311
#define SIG_UART1_TRANS _VECTOR(18)
312
313
/* EEPROM Ready */
314
#define EE_RDY_vect _VECTOR(19)
315
#define SIG_EEPROM_READY _VECTOR(19)
316
317
/* Analog Comparator */
318
#define ANA_COMP_vect _VECTOR(20)
319
#define SIG_COMPARATOR _VECTOR(20)
320
321
#define _VECTORS_SIZE 84
322
323
/* Bit numbers */
324
325
/* GIMSK */
326
#define INT1 7
327
#define INT0 6
328
#define INT2 5
329
330
/* GIFR */
331
#define INTF1 7
332
#define INTF0 6
333
#define INTF2 5
334
335
/* TIMSK */
336
#define TOIE1 7
337
#define OCIE1A 6
338
#define OCIE1B 5
339
#define TOIE2 4
340
#define TICIE1 3
341
#define OCIE2 2
342
#define TOIE0 1
343
#define OCIE0 0
344
345
/* TIFR */
346
#define TOV1 7
347
#define OCF1A 6
348
#define OCF1B 5
349
#define TOV2 4
350
#define ICF1 3
351
#define OCF2 2
352
#define TOV0 1
353
#define OCF0 0
354
355
/* MCUCR */
356
#define SRE 7
357
#define SRW10 6
358
#define SE 5
359
#define SM1 4
360
#define ISC11 3
361
#define ISC10 2
362
#define ISC01 1
363
#define ISC00 0
364
365
/* EMCUCR */
366
#define SM0 7
367
#define SRL2 6
368
#define SRL1 5
369
#define SRL0 4
370
#define SRW01 3
371
#define SRW00 2
372
#define SRW11 1
373
#define ISC2 0
374
375
/* SPMCR */
376
#define BLBSET 3
377
#define PGWRT 2
378
#define PGERS 1
379
#define SPMEN 0
380
381
/* SFIOR */
382
#define PSR2 1
383
#define PSR10 0
384
385
/* TCCR0 */
386
#define FOC0 7
387
#define PWM0 6
388
#define COM01 5
389
#define COM00 4
390
#define CTC0 3
391
#define CS02 2
392
#define CS01 1
393
#define CS00 0
394
395
/* TCCR2 */
396
#define FOC2 7
397
#define PWM2 6
398
#define COM21 5
399
#define COM20 4
400
#define CTC2 3
401
#define CS22 2
402
#define CS21 1
403
#define CS20 0
404
405
/* ASSR */
406
#define AS2 3
407
#define TCN2UB 2
408
#define OCR2UB 1
409
#define TCR2UB 0
410
411
/* TCCR1A */
412
#define COM1A1 7
413
#define COM1A0 6
414
#define COM1B1 5
415
#define COM1B0 4
416
#define FOC1A 3
417
#define FOC1B 2
418
#define PWM11 1
419
#define PWM10 0
420
421
/* TCCR1B */
422
#define ICNC1 7
423
#define ICES1 6
424
#define CTC1 3
425
#define CS12 2
426
#define CS11 1
427
#define CS10 0
428
429
/* WDTCR */
430
#define WDTOE 4
431
#define WDE 3
432
#define WDP2 2
433
#define WDP1 1
434
#define WDP0 0
435
436
/* PORTA */
437
#define PA7 7
438
#define PA6 6
439
#define PA5 5
440
#define PA4 4
441
#define PA3 3
442
#define PA2 2
443
#define PA1 1
444
#define PA0 0
445
446
/* DDRA */
447
#define DDA7 7
448
#define DDA6 6
449
#define DDA5 5
450
#define DDA4 4
451
#define DDA3 3
452
#define DDA2 2
453
#define DDA1 1
454
#define DDA0 0
455
456
/* PINA */
457
#define PINA7 7
458
#define PINA6 6
459
#define PINA5 5
460
#define PINA4 4
461
#define PINA3 3
462
#define PINA2 2
463
#define PINA1 1
464
#define PINA0 0
465
466
/*
467
PB7 = SCK
468
PB6 = MISO
469
PB5 = MOSI
470
PB4 = SS#
471
PB3 = TXD1 / AIN1
472
PB2 = RXD1 / AIN0
473
PB1 = OC2 / T1
474
PB0 = OC0 / T0
475
*/
476
477
/* PORTB */
478
#define PB7 7
479
#define PB6 6
480
#define PB5 5
481
#define PB4 4
482
#define PB3 3
483
#define PB2 2
484
#define PB1 1
485
#define PB0 0
486
487
/* DDRB */
488
#define DDB7 7
489
#define DDB6 6
490
#define DDB5 5
491
#define DDB4 4
492
#define DDB3 3
493
#define DDB2 2
494
#define DDB1 1
495
#define DDB0 0
496
497
/* PINB */
498
#define PINB7 7
499
#define PINB6 6
500
#define PINB5 5
501
#define PINB4 4
502
#define PINB3 3
503
#define PINB2 2
504
#define PINB1 1
505
#define PINB0 0
506
507
/* PORTC */
508
#define PC7 7
509
#define PC6 6
510
#define PC5 5
511
#define PC4 4
512
#define PC3 3
513
#define PC2 2
514
#define PC1 1
515
#define PC0 0
516
517
/* DDRC */
518
#define DDC7 7
519
#define DDC6 6
520
#define DDC5 5
521
#define DDC4 4
522
#define DDC3 3
523
#define DDC2 2
524
#define DDC1 1
525
#define DDC0 0
526
527
/* PINC */
528
#define PINC7 7
529
#define PINC6 6
530
#define PINC5 5
531
#define PINC4 4
532
#define PINC3 3
533
#define PINC2 2
534
#define PINC1 1
535
#define PINC0 0
536
537
/*
538
PD7 = RD#
539
PD6 = WR#
540
PD5 = TOSC2 / OC1A
541
PD4 = TOSC1
542
PD3 = INT1
543
PD2 = INT0
544
PD1 = TXD0
545
PD0 = RXD0
546
*/
547
548
/* PORTD */
549
#define PD7 7
550
#define PD6 6
551
#define PD5 5
552
#define PD4 4
553
#define PD3 3
554
#define PD2 2
555
#define PD1 1
556
#define PD0 0
557
558
/* DDRD */
559
#define DDD7 7
560
#define DDD6 6
561
#define DDD5 5
562
#define DDD4 4
563
#define DDD3 3
564
#define DDD2 2
565
#define DDD1 1
566
#define DDD0 0
567
568
/* PIND */
569
#define PIND7 7
570
#define PIND6 6
571
#define PIND5 5
572
#define PIND4 4
573
#define PIND3 3
574
#define PIND2 2
575
#define PIND1 1
576
#define PIND0 0
577
578
/*
579
PE2 = ALE
580
PE1 = OC1B
581
PE0 = ICP / INT2
582
*/
583
584
/* PORTE */
585
#define PE2 2
586
#define PE1 1
587
#define PE0 0
588
589
/* DDRE */
590
#define DDE2 2
591
#define DDE1 1
592
#define DDE0 0
593
594
/* PINE */
595
#define PINE2 2
596
#define PINE1 1
597
#define PINE0 0
598
599
/* SPSR */
600
#define SPIF 7
601
#define WCOL 6
602
#define SPI2X 0
603
604
/* SPCR */
605
#define SPIE 7
606
#define SPE 6
607
#define DORD 5
608
#define MSTR 4
609
#define CPOL 3
610
#define CPHA 2
611
#define SPR1 1
612
#define SPR0 0
613
614
/* UCSR0A, UCSR1A */
615
#define RXC 7
616
#define TXC 6
617
#define UDRE 5
618
#define FE 4
619
#define DOR 3
620
#define U2X 1
621
#define MPCM 0
622
623
/* UCSR0B, UCSR1B */
624
#define RXCIE 7
625
#define TXCIE 6
626
#define UDRIE 5
627
#define RXEN 4
628
#define TXEN 3
629
#define CHR9 2
630
#define RXB8 1
631
#define TXB8 0
632
633
/* ACSR */
634
#define ACD 7
635
#define AINBG 6
636
#define ACO 5
637
#define ACI 4
638
#define ACIE 3
639
#define ACIC 2
640
#define ACIS1 1
641
#define ACIS0 0
642
643
/* EEPROM Control Register */
644
#define EERIE 3
645
#define EEMWE 2
646
#define EEWE 1
647
#define EERE 0
648
649
/* Constants */
650
#define SPM_PAGESIZE 128
651
#define RAMEND 0x45F
652
#define XRAMEND 0xFFFF
653
#define E2END 0x1FF
654
#define E2PAGESIZE 0
655
#define FLASHEND 0x3FFF
656
657
658
/* Fuses */
659
660
#define FUSE_MEMORY_SIZE 1
661
662
/* Fuse Byte */
663
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
664
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
665
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
666
#define FUSE_SUT (unsigned char)~_BV(4)
667
#define FUSE_SPIEN (unsigned char)~_BV(5)
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#define FUSE_BOOTRST (unsigned char)~_BV(6)
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#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN)
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/* Lock Bits */
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#define __LOCK_BITS_EXIST
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#define __BOOT_LOCK_BITS_0_EXIST
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#define __BOOT_LOCK_BITS_1_EXIST
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/* Signature */
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#define SIGNATURE_0 0x1E
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#define SIGNATURE_1 0x94
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#define SIGNATURE_2 0x01
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#endif
/* _AVR_IOM161_H_ */
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