RTEMS Documentation Project RTEMS CPU Architecture Supplement
  • 1. Preface
  • 2. Port Specific Information
    • 2.1. CPU Model Dependent Features
      • 2.1.1. CPU Model Name
      • 2.1.2. Floating Point Unit
    • 2.2. Multilibs
    • 2.3. Calling Conventions
      • 2.3.1. Calling Mechanism
      • 2.3.2. Register Usage
      • 2.3.3. Parameter Passing
      • 2.3.4. User-Provided Routines
    • 2.4. Memory Model
      • 2.4.1. Flat Memory Model
    • 2.5. Interrupt Processing
      • 2.5.1. Vectoring of an Interrupt Handler
      • 2.5.2. Interrupt Levels
      • 2.5.3. Disabling of Interrupts by RTEMS
    • 2.6. Symmetric Multiprocessing
    • 2.7. Thread-Local Storage
    • 2.8. CPU counter
    • 2.9. Interrupt Profiling
    • 2.10. Board Support Packages
      • 2.10.1. System Reset
  • 3. AArch64 Specific Information
    • 3.1. CPU Model Dependent Features
      • 3.1.1. CPU Model Name
      • 3.1.2. Floating Point Unit and SIMD
    • 3.2. Multilibs
    • 3.3. Calling Conventions
    • 3.4. Memory Model
    • 3.5. Interrupt Processing
      • 3.5.1. Interrupt Levels
      • 3.5.2. Interrupt Stack
    • 3.6. Symmetric Multiprocessing
    • 3.7. Thread-Local Storage
  • 4. ARM Specific Information
    • 4.1. CPU Model Dependent Features
      • 4.1.1. CPU Model Name
      • 4.1.2. Count Leading Zeroes Instruction
      • 4.1.3. Floating Point Unit
    • 4.2. Multilibs
    • 4.3. Calling Conventions
    • 4.4. Memory Model
    • 4.5. Interrupt Processing
      • 4.5.1. Interrupt Levels
      • 4.5.2. Interrupt Stack
    • 4.6. Symmetric Multiprocessing
    • 4.7. Thread-Local Storage
  • 5. Atmel AVR Specific Information
    • 5.1. CPU Model Dependent Features
      • 5.1.1. Count Leading Zeroes Instruction
    • 5.2. Calling Conventions
      • 5.2.1. Processor Background
      • 5.2.2. Register Usage
      • 5.2.3. Parameter Passing
    • 5.3. Memory Model
    • 5.4. Interrupt Processing
      • 5.4.1. Vectoring of an Interrupt Handler
      • 5.4.2. Disabling of Interrupts by RTEMS
      • 5.4.3. Interrupt Stack
    • 5.5. Symmetric Multiprocessing
    • 5.6. Thread-Local Storage
    • 5.7. Board Support Packages
      • 5.7.1. System Reset
  • 6. Blackfin Specific Information
    • 6.1. CPU Model Dependent Features
      • 6.1.1. Count Leading Zeroes Instruction
    • 6.2. Calling Conventions
      • 6.2.1. Processor Background
      • 6.2.2. Register Usage
      • 6.2.3. Parameter Passing
    • 6.3. Memory Model
    • 6.4. Interrupt Processing
      • 6.4.1. Vectoring of an Interrupt Handler
      • 6.4.2. Disabling of Interrupts by RTEMS
      • 6.4.3. Interrupt Stack
    • 6.5. Symmetric Multiprocessing
    • 6.6. Thread-Local Storage
    • 6.7. Board Support Packages
      • 6.7.1. System Reset
  • 7. Epiphany Specific Information
  • 8. Intel/AMD x86 Specific Information
    • 8.1. CPU Model Dependent Features
      • 8.1.1. bswap Instruction
    • 8.2. Calling Conventions
      • 8.2.1. Processor Background
      • 8.2.2. Calling Mechanism
      • 8.2.3. Register Usage
      • 8.2.4. Parameter Passing
    • 8.3. Memory Model
      • 8.3.1. Flat Memory Model
    • 8.4. Interrupt Processing
      • 8.4.1. Vectoring of Interrupt Handler
      • 8.4.2. Interrupt Stack Frame
      • 8.4.3. Interrupt Levels
      • 8.4.4. Interrupt Stack
    • 8.5. Symmetric Multiprocessing
    • 8.6. Thread-Local Storage
    • 8.7. Board Support Packages
      • 8.7.1. System Reset
      • 8.7.2. Processor Initialization
  • 9. Lattice Mico32 Specific Information
    • 9.1. CPU Model Dependent Features
    • 9.2. Register Architecture
    • 9.3. Calling Conventions
      • 9.3.1. Calling Mechanism
      • 9.3.2. Register Usage
      • 9.3.3. Parameter Passing
    • 9.4. Memory Model
    • 9.5. Interrupt Processing
    • 9.6. Symmetric Multiprocessing
    • 9.7. Thread-Local Storage
    • 9.8. Board Support Packages
      • 9.8.1. System Reset
  • 10. Renesas M32C Specific Information
  • 11. M68xxx and Coldfire Specific Information
    • 11.1. CPU Model Dependent Features
      • 11.1.1. BFFFO Instruction
      • 11.1.2. Vector Base Register
      • 11.1.3. Separate Stacks
      • 11.1.4. Pre-Indexing Address Mode
      • 11.1.5. Extend Byte to Long Instruction
    • 11.2. Calling Conventions
      • 11.2.1. Calling Mechanism
      • 11.2.2. Register Usage
      • 11.2.3. Parameter Passing
    • 11.3. Memory Model
    • 11.4. Interrupt Processing
      • 11.4.1. Vectoring of an Interrupt Handler
        • 11.4.1.1. Models Without Separate Interrupt Stacks
        • 11.4.1.2. Models With Separate Interrupt Stacks
      • 11.4.2. CPU Models Without VBR and RAM at 0
      • 11.4.3. Interrupt Levels
    • 11.5. Symmetric Multiprocessing
    • 11.6. Thread-Local Storage
    • 11.7. Board Support Packages
      • 11.7.1. System Reset
      • 11.7.2. Processor Initialization
  • 12. Xilinx MicroBlaze Specific Information
    • 12.1. CPU Model Dependent Features
    • 12.2. Calling Conventions
    • 12.3. Interrupt Processing
      • 12.3.1. Interrupt Levels
      • 12.3.2. Interrupt Stack
    • 12.4. Symmetric Multiprocessing
    • 12.5. Thread-Local Storage
  • 13. MIPS Specific Information
    • 13.1. CPU Model Dependent Features
      • 13.1.1. Another Optional Feature
    • 13.2. Calling Conventions
      • 13.2.1. Processor Background
      • 13.2.2. Calling Mechanism
      • 13.2.3. Register Usage
      • 13.2.4. Parameter Passing
    • 13.3. Memory Model
      • 13.3.1. Flat Memory Model
    • 13.4. Interrupt Processing
      • 13.4.1. Vectoring of an Interrupt Handler
      • 13.4.2. Interrupt Levels
    • 13.5. Symmetric Multiprocessing
    • 13.6. Thread-Local Storage
    • 13.7. Board Support Packages
      • 13.7.1. System Reset
      • 13.7.2. Processor Initialization
  • 14. Altera Nios II Specific Information
    • 14.1. Symmetric Multiprocessing
    • 14.2. Thread-Local Storage
  • 15. OpenRISC 1000 Specific Information
    • 15.1. Calling Conventions
      • 15.1.1. Floating Point Unit
    • 15.2. Memory Model
    • 15.3. Interrupt Processing
      • 15.3.1. Interrupt Levels
      • 15.3.2. Interrupt Stack
    • 15.4. Symmetric Multiprocessing
  • 16. PowerPC Specific Information
    • 16.1. Multilibs
    • 16.2. Application Binary Interface
    • 16.3. Special Registers
    • 16.4. Memory Model
    • 16.5. Interrupt Processing
      • 16.5.1. Interrupt Levels
      • 16.5.2. Interrupt Stack
    • 16.6. Symmetric Multiprocessing
    • 16.7. Thread-Local Storage
    • 16.8. 64-bit Caveats
  • 17. RISC-V Specific Information
    • 17.1. Calling Conventions
    • 17.2. Multilibs
    • 17.3. Interrupt Processing
      • 17.3.1. Interrupt Levels
      • 17.3.2. Interrupt Stack
    • 17.4. Symmetric Multiprocessing
    • 17.5. Thread-Local Storage
  • 18. SuperH Specific Information
    • 18.1. CPU Model Dependent Features
      • 18.1.1. Another Optional Feature
    • 18.2. Calling Conventions
      • 18.2.1. Calling Mechanism
      • 18.2.2. Register Usage
      • 18.2.3. Parameter Passing
    • 18.3. Memory Model
      • 18.3.1. Flat Memory Model
    • 18.4. Interrupt Processing
      • 18.4.1. Vectoring of an Interrupt Handler
      • 18.4.2. Interrupt Levels
    • 18.5. Symmetric Multiprocessing
    • 18.6. Thread-Local Storage
    • 18.7. Board Support Packages
      • 18.7.1. System Reset
      • 18.7.2. Processor Initialization
  • 19. SPARC Specific Information
    • 19.1. CPU Model Dependent Features
      • 19.1.1. CPU Model Feature Flags
        • 19.1.1.1. CPU Model Name
        • 19.1.1.2. Floating Point Unit
        • 19.1.1.3. Bitscan Instruction
        • 19.1.1.4. Number of Register Windows
        • 19.1.1.5. Low Power Mode
      • 19.1.2. CPU Model Implementation Notes
    • 19.2. Calling Conventions
      • 19.2.1. Programming Model
        • 19.2.1.1. Non-Floating Point Registers
        • 19.2.1.2. Floating Point Registers
        • 19.2.1.3. Special Registers
      • 19.2.2. Register Windows
      • 19.2.3. Call and Return Mechanism
      • 19.2.4. Calling Mechanism
      • 19.2.5. Register Usage
      • 19.2.6. Parameter Passing
      • 19.2.7. User-Provided Routines
    • 19.3. Memory Model
      • 19.3.1. Flat Memory Model
    • 19.4. Interrupt Processing
      • 19.4.1. Synchronous Versus Asynchronous Traps
      • 19.4.2. Trap Table
      • 19.4.3. Vectoring of Interrupt Handler
      • 19.4.4. Traps and Register Windows
      • 19.4.5. Interrupt Levels
      • 19.4.6. Disabling of Interrupts by RTEMS
      • 19.4.7. Interrupt Stack
    • 19.5. Symmetric Multiprocessing
    • 19.6. Thread-Local Storage
    • 19.7. Board Support Packages
      • 19.7.1. System Reset
      • 19.7.2. Processor Initialization
    • 19.8. Stacks and Register Windows
      • 19.8.1. General Structure
      • 19.8.2. Register Semantics
      • 19.8.3. Register Windows and the Stack
      • 19.8.4. Procedure epilogue and prologue
      • 19.8.5. Procedures, stacks, and debuggers
      • 19.8.6. The window overflow and underflow traps
  • 20. SPARC-64 Specific Information
    • 20.1. CPU Model Dependent Features
      • 20.1.1. CPU Model Feature Flags
        • 20.1.1.1. CPU Model Name
        • 20.1.1.2. Floating Point Unit
        • 20.1.1.3. Number of Register Windows
      • 20.1.2. CPU Model Implementation Notes
        • 20.1.2.1. sun4u Notes
      • 20.1.3. sun4v Notes
    • 20.2. Calling Conventions
      • 20.2.1. Programming Model
        • 20.2.1.1. Non-Floating Point Registers
        • 20.2.1.2. Floating Point Registers
        • 20.2.1.3. Special Registers
      • 20.2.2. Register Windows
      • 20.2.3. Call and Return Mechanism
      • 20.2.4. Calling Mechanism
      • 20.2.5. Register Usage
      • 20.2.6. Parameter Passing
      • 20.2.7. User-Provided Routines
    • 20.3. Memory Model
      • 20.3.1. Flat Memory Model
    • 20.4. Interrupt Processing
      • 20.4.1. Synchronous Versus Asynchronous Traps
      • 20.4.2. Vectoring of Interrupt Handler
      • 20.4.3. Traps and Register Windows
      • 20.4.4. Interrupt Levels
      • 20.4.5. Disabling of Interrupts by RTEMS
      • 20.4.6. Interrupt Stack
    • 20.5. Symmetric Multiprocessing
    • 20.6. Thread-Local Storage
    • 20.7. Board Support Packages
      • 20.7.1. HelenOS and Open Firmware
  • 21. References
Index
RTEMS CPU Architecture Supplement
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