13. MIPS Specific Information¶
This chapter discusses the MIPS architecture dependencies in this port of RTEMS. The MIPS family has a wide variety of implementations by a wide range of vendors. Consequently, there are many, many CPU models within it.
Architecture Documents
IDT docs are online at http://www.idt.com/products/risc/Welcome.html
13.1. CPU Model Dependent Features¶
This section presents the set of features which vary across MIPS
implementations and are of importance to RTEMS. The set of CPU model feature
macros are defined in the file cpukit/score/cpu/mips/mips.h
based upon the
particular CPU model specified on the compilation command line.
13.1.1. Another Optional Feature¶
The macro XXX
13.2. Calling Conventions¶
13.2.1. Processor Background¶
TBD
13.2.2. Calling Mechanism¶
TBD
13.2.3. Register Usage¶
TBD
13.2.4. Parameter Passing¶
TBD
13.3. Memory Model¶
13.3.1. Flat Memory Model¶
The MIPS family supports a flat 32-bit address space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a 32-bit value and is byte addressable. The address may be used to reference a single byte, word (2-bytes), or long word (4 bytes). Memory accesses within this address space are performed in big endian fashion by the processors in this family.
Some of the MIPS family members such as the support virtual memory and segmentation. RTEMS does not support virtual memory or segmentation on any of these family members.
13.4. Interrupt Processing¶
Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor’s unique architecture. Discussed in this chapter are the MIPS’s interrupt response and control mechanisms as they pertain to RTEMS.
13.4.1. Vectoring of an Interrupt Handler¶
Upon receipt of an interrupt the XXX family members with separate interrupt stacks automatically perform the following actions:
TBD
A nested interrupt is processed similarly by these CPU models with the exception that only a single ISF is placed on the interrupt stack and the current stack need not be switched.
13.4.2. Interrupt Levels¶
TBD
13.5. Symmetric Multiprocessing¶
SMP is not supported.
13.6. Thread-Local Storage¶
Thread-local storage is not implemented.
13.7. Board Support Packages¶
13.7.1. System Reset¶
An RTEMS based application is initiated or re-initiated when the processor is reset. When the processor is reset, it performs the following actions:
TBD
13.7.2. Processor Initialization¶
TBD