RTEMS Documentation Project RTEMS CPU Architecture Supplement

1. Preface
2. Port Specific Information
3. AArch64 Specific Information
4. ARM Specific Information
5. Atmel AVR Specific Information
6. Blackfin Specific Information
7. Epiphany Specific Information
8. Intel/AMD x86 Specific Information
9. Lattice Mico32 Specific Information
10. Renesas M32C Specific Information
11. M68xxx and Coldfire Specific Information
12. Xilinx MicroBlaze Specific Information
13. MIPS Specific Information
14. Altera Nios II Specific Information
- 14.1. Symmetric Multiprocessing
- 14.2. Thread-Local Storage
15. OpenRISC 1000 Specific Information
16. PowerPC Specific Information
17. RISC-V Specific Information
18. SuperH Specific Information
19. SPARC Specific Information
20. SPARC-64 Specific Information
21. References

Index

RTEMS CPU Architecture Supplement

7. Epiphany Specific Information

7. Epiphany Specific Information¶

Due to an unmaintained toolchain (internal errors in GCC, no FSF GDB integration) the Epiphany architecture was obsoleted in RTEMS 5.1 and removed in RTEMS 6.1.

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