RTEMS Logo

RTEMS 4.7.0 On-Line Library


Intel/AMD x86 Specific Information Interrupt Processing

PREV UP NEXT Bookshelf RTEMS CPU Architecture Supplement

2.4: Interrupt Processing

  • Intel/AMD x86 Specific Information Vectoring of Interrupt Handler
  • Intel/AMD x86 Specific Information Interrupt Stack Frame
  • Intel/AMD x86 Specific Information Interrupt Levels
  • Intel/AMD x86 Specific Information Disabling of Interrupts by RTEMS
  • Intel/AMD x86 Specific Information Interrupt Stack
  • Different types of processors respond to the occurrence of an interrupt in their own unique fashion. In addition, each processor type provides a control mechanism to allow the proper handling of an interrupt. The processor dependent response to the interrupt modifies the execution state and results in the modification of the execution stream. This modification usually requires that an interrupt handler utilize the provided control mechanisms to return to the normal processing stream. Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's unique architecture. Discussed in this chapter are the the processor's response and control mechanisms as they pertain to RTEMS.


    PREV UP NEXT Bookshelf RTEMS CPU Architecture Supplement

    Copyright © 1988-2004 OAR Corporation