RTEMS CPU Architecture Supplement
The SPARC architecture defines thirty-two non-floating point registers directly visible to the programmer. These are divided into four sets:
Each register is referred to by either two or three names in the SPARC reference manuals. First, the registers are referred to as r0 through r31 or with the alternate notation r[0] through r[31]. Second, each register is a member of one of the four sets listed above. Finally, some registers have an architecturally defined role in the programming model which provides an alternate name. The following table describes the mapping between the 32 registers and the register sets:
| Register Number | Register Names | Description |
| 0 - 7 | g0 - g7 | Global Registers |
| 8 - 15 | o0 - o7 | Output Registers |
| 16 - 23 | l0 - l7 | Local Registers |
| 24 - 31 | i0 - i7 | Input Registers |
As mentioned above, some of the registers serve defined roles in the programming model. The following table describes the role of each of these registers:
| Register Name | Alternate Name | Description |
| g0 | NA | reads return 0 ; writes are ignored |
| o6 | sp | stack pointer |
| i6 | fp | frame pointer |
| i7 | NA | return address |
RTEMS CPU Architecture Supplement
Copyright © 1988-2004 OAR Corporation