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RTEMS 4.6.99.3 On-Line Library


Task Context Management CPU_HAS_FPU Macro Definition

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6.4.1: CPU_HAS_FPU Macro Definition

The CPU_HAS_FPU macro is set based on the answer to the question: Does the CPU have hardware floating point? If the CPU has an FPU, then this should be set to TRUE. Otherwise, it should be set to FALSE. The primary implication of setting this macro to TRUE is that it indicates that tasks may have floating point contexts. In the Classic API, this means that the RTEMS_FLOATING_POINT task attribute specified as part of rtems_task_create is supported on this CPU. If CPU_HAS_FPU is set to FALSE, then no tasks or threads may be floating point and the RTEMS_FLOATING_POINT task attribute is ignored. On an API such as POSIX where all threads implicitly have a floating point context, then the setting of this macro determines whether every POSIX thread has a floating point context.

The following example illustrates how the CPU_HARDWARE_FP (XXX macro name is varying) macro is set based on the CPU family dependent macro.

#if ( THIS_CPU_FAMILY_HAS_FPU == 1 ) /* where THIS_CPU_FAMILY */
                                     /* might be M68K */
#define CPU_HARDWARE_FP     TRUE
#else
#define CPU_HARDWARE_FP     FALSE
#endif

The macro name THIS_CPU_FAMILY_HAS_FPU should be made CPU specific. It indicates whether or not this CPU model has FP support. For example, the definition of the i386ex and i386sx CPU models would set I386_HAS_FPU to FALSE to indicate that these CPU models are i386's without an i387 and wish to leave floating point support out of RTEMS when built for the i386_nofp processor model. On a CPU with a built-in FPU like the i486, this would be defined as TRUE.

On some processor families, the setting of the THIS_CPU_FAMILY_HAS_FPU macro may be derived from compiler predefinitions. This can be used when the compiler distinguishes the individual CPU models for this CPU family as distinctly as RTEMS requires. Often RTEMS needs to need more about the CPU model than the compiler because of differences at the system level such as caching, interrupt structure.


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