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RTEMS 4.10.2 On-Line Library


Lattice Mico32 Specific Information

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Chapter 6: Lattice Mico32 Specific Information

  • Lattice Mico32 Specific Information CPU Model Dependent Features
  • Lattice Mico32 Specific Information Register Architecture
  • Lattice Mico32 Specific Information Calling Conventions
  • Lattice Mico32 Specific Information Memory Model
  • Lattice Mico32 Specific Information Interrupt Processing
  • Lattice Mico32 Specific Information Default Fatal Error Processing
  • Lattice Mico32 Specific Information Board Support Packages
  • This chaper discusses the Lattice Mico32 architecture dependencies in this port of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement. Although mainly targeted for Lattice FPGA devices the microprocessor can be implemented on other vendors' FPGAs, too.

    Architecture Documents

    For information on the Lattice Mico32 architecture, refer to the following documents available from Lattice Semiconductor `http://www.latticesemi.com/'.


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