RTEMS Hewlett Packard PA-RISC Applications Supplement
Two levels (enabled and disabled) of interrupt priorities are supported by the PA-RISC architecture. Level zero (0) indicates that interrupts are fully enabled (i.e. the I bit of the PSW is 1). Level one (1) indicates that interrupts are disabled (i.e. the I bit of the PSW is 0). Thirty-two independent sources of external interrupts are supported by the PA-RISC architecture. Each of these interrupts sources may be individually enabled or disabled. When processor interrupts are disabled, all sources of external interrupts are ignored. When processor interrupts are enabled, the EIR (External Interrupt Request) register is used to determine which sources are currently allowed to generate interrupts.
Although RTEMS supports 256 interrupt levels, the PA-RISC architecture only supports two. RTEMS interrupt level 0 indicates that interrupts are enabled and level 1 indicates that interrupts are disabled. All other RTEMS interrupt levels are undefined and their behavior is unpredictable.
RTEMS Hewlett Packard PA-RISC Applications Supplement
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