Intel I386 CPU Dependent Source. More...

#include <string.h>
#include <rtems/score/types.h>
#include <rtems/score/i386.h>
#include <rtems/score/interrupts.h>
#include <rtems/score/registers.h>

Include dependency graph for cpu.h:

Go to the source code of this file.

Data Structures
struct	Context_Control
	This defines the minimal set of integer and processor state registers that must be saved during a voluntary context switch from one thread to another. More...

struct	Context_Control_fp
	This defines the complete set of floating point registers that must be saved during any context switch from one thread to another. More...

struct	CPU_Exception_frame
	The set of registers that specifies the complete processor state. More...

Macros
#define	CPU_INLINE_ENABLE_DISPATCH TRUE

#define	CPU_SIMPLE_VECTORED_INTERRUPTS FALSE

#define	CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE

#define	CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE

#define	CPU_ALLOCATE_INTERRUPT_STACK TRUE

#define	CPU_ISR_PASSES_FRAME_POINTER 0

#define	CPU_HARDWARE_FP FALSE

#define	CPU_SOFTWARE_FP FALSE

#define	CPU_ALL_TASKS_ARE_FP FALSE

#define	CPU_IDLE_TASK_IS_FP FALSE

#define	CPU_USE_DEFERRED_FP_SWITCH TRUE

#define	CPU_STACK_GROWS_UP FALSE

#define	CPU_STRUCTURE_ALIGNMENT

#define	CPU_TIMESTAMP_USE_INT64_INLINE TRUE

#define	CPU_PROVIDES_IDLE_THREAD_BODY TRUE

#define	CPU_BIG_ENDIAN FALSE

#define	CPU_LITTLE_ENDIAN TRUE

#define	CPU_PER_CPU_CONTROL_SIZE 0

#define	I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0

#define	I386_CONTEXT_CONTROL_ESP_OFFSET 4

#define	I386_CONTEXT_CONTROL_EBP_OFFSET 8

#define	I386_CONTEXT_CONTROL_EBX_OFFSET 12

#define	I386_CONTEXT_CONTROL_ESI_OFFSET 16

#define	I386_CONTEXT_CONTROL_EDI_OFFSET 20

#define	_CPU_Context_Get_SP(_context) (_context)->esp

#define	CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )

#define	CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */

#define	CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */

#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

#define	CPU_STACK_MINIMUM_SIZE 4096

#define	CPU_SIZEOF_POINTER 4

#define	CPU_ALIGNMENT 4

#define	CPU_HEAP_ALIGNMENT CPU_ALIGNMENT

#define	CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT

#define	CPU_STACK_ALIGNMENT 16

#define	_CPU_ISR_Disable(_level) i386_disable_interrupts( _level )

#define	_CPU_ISR_Enable(_level) i386_enable_interrupts( _level )

#define	_CPU_ISR_Flash(_level) i386_flash_interrupts( _level )

#define	_CPU_ISR_Set_level(_new_level)

#define	_CPU_Interrupt_stack_setup(_lo, _hi)

#define	CPU_EFLAGS_INTERRUPTS_ON 0x00003202

#define	CPU_EFLAGS_INTERRUPTS_OFF 0x00003002

#define	_CPU_Context_Initialize(_the_context, _stack_base, _size, _isr, _entry_point, _is_fp, _tls_area)

#define	_CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) );

#define	_CPU_Context_Fp_start(_base, _offset) ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )

#define	_CPU_Context_Initialize_fp(_fp_area)

#define	_CPU_Fatal_halt(_source, _error)

#define	CPU_USE_GENERIC_BITFIELD_CODE FALSE

#define	CPU_USE_GENERIC_BITFIELD_DATA FALSE

#define	_CPU_Bitfield_Find_first_bit(_value, _output)

#define	_CPU_Priority_Mask(_bit_number) ( 1 << (_bit_number) )

#define	_CPU_Priority_bits_index(_priority) (_priority)

Typedefs
typedef void(*	cpuExcHandlerType) (CPU_Exception_frame *)

typedef void	CPU_Interrupt_frame

typedef uint32_t	CPU_Counter_ticks

Enumerations
enum	Intel_symbolic_exception_name { I386_EXCEPTION_DIVIDE_BY_ZERO = 0, I386_EXCEPTION_DEBUG = 1, I386_EXCEPTION_NMI = 2, I386_EXCEPTION_BREAKPOINT = 3, I386_EXCEPTION_OVERFLOW = 4, I386_EXCEPTION_BOUND = 5, I386_EXCEPTION_ILLEGAL_INSTR = 6, I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, I386_EXCEPTION_DOUBLE_FAULT = 8, I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, I386_EXCEPTION_INVALID_TSS = 10, I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, I386_EXCEPTION_GENERAL_PROT_ERR = 13, I386_EXCEPTION_PAGE_FAULT = 14, I386_EXCEPTION_INTEL_RES15 = 15, I386_EXCEPTION_FLOAT_ERROR = 16, I386_EXCEPTION_ALIGN_CHECK = 17, I386_EXCEPTION_MACHINE_CHECK = 18, I386_EXCEPTION_ENTER_RDBG = 50 }

Functions
void	rtems_exception_init_mngt (void)

uint32_t	_CPU_ISR_Get_level (void)
	Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode. More...

void	_CPU_Initialize (void)
	CPU initialization. More...

void	_CPU_ISR_install_raw_handler (uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
	This routine installs a "raw" interrupt handler directly into the processor's vector table. More...

void	_CPU_ISR_install_vector (uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
	This routine installs an interrupt vector. More...

void *	_CPU_Thread_Idle_body (uintptr_t ignored)
	This routine is the CPU dependent IDLE thread body. More...

void	_CPU_Context_switch (Context_Control run, Context_Control heir)
	CPU switch context. More...

void	_CPU_Context_restore (Context_Control *new_context)
	This routine is generally used only to restart self in an efficient manner. More...

void	_CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)
	This routine saves the floating point context passed to it. More...

void	_CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)
	This routine restores the floating point context passed to it. More...

void	_CPU_Exception_frame_print (const CPU_Exception_frame *frame)
	Prints the exception frame via printk(). More...

CPU_Counter_ticks	_CPU_Counter_read (void)

Variables
cpuExcHandlerType	_currentExcHandler

SCORE_EXTERN Context_Control_fp	_CPU_Null_fp_context

Detailed Description

Intel I386 CPU Dependent Source.

This include file contains information pertaining to the Intel i386 processor.

Macro Definition Documentation

◆ _CPU_Bitfield_Find_first_bit

#define _CPU_Bitfield_Find_first_bit	(	_value,
		_output
	)

Value:

{ \
    register uint16_t   __value_in_register = (_value); \
    \
    _output = 0; \
    \
    __asm__ volatile ( "bsfw    %0,%1 " \
                    : "=r" (__value_in_register), "=r" (_output) \
                    : "0"  (__value_in_register), "1"  (_output) \
    ); \
  }

◆ _CPU_Context_Initialize

#define _CPU_Context_Initialize	(	_the_context,
		_stack_base,
		_size,
		_isr,
		_entry_point,
		_is_fp,
		_tls_area
	)

Value:

do { \
    uint32_t   _stack; \
    \
    (void) _is_fp; /* avoid warning for being unused */ \
    if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \
    else          (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \
    \
    _stack  = ((uint32_t)(_stack_base)) + (_size); \
        _stack &= ~ (CPU_STACK_ALIGNMENT - 1); \
    _stack -= 2*sizeof(proc_ptr*); /* see above for why we need to do this */ \
    *((proc_ptr *)(_stack)) = (_entry_point); \
    (_the_context)->ebp     = (void *) 0; \
    (_the_context)->esp     = (void *) _stack; \
  } while (0)

◆ _CPU_Context_Initialize_fp

#define _CPU_Context_Initialize_fp ( _fp_area )

Value:

{ \
    memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \
  }

◆ _CPU_Fatal_halt

#define _CPU_Fatal_halt	(	_source,
		_error
	)

Value:

{ \
    uint32_t _error_lvalue = ( _error ); \
    __asm__ volatile ( "cli ; \                    movl %0,%%eax ; \                    hlt" \
                    : "=r" ((_error_lvalue)) : "0" ((_error_lvalue)) \
    ); \
  }

◆ _CPU_Interrupt_stack_setup

#define _CPU_Interrupt_stack_setup	(	_lo,
		_hi
	)

Value:

do {                                        \
                _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \
        } while (0)

◆ _CPU_ISR_Set_level

#define _CPU_ISR_Set_level ( _new_level )

Value:

{ \
    if ( _new_level ) __asm__ volatile ( "cli" ); \
    else              __asm__ volatile ( "sti" ); \
  }

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ _CPU_Bitfield_Find_first_bit

◆ _CPU_Context_Initialize

◆ _CPU_Context_Initialize_fp

◆ _CPU_Fatal_halt

◆ _CPU_Interrupt_stack_setup

◆ _CPU_ISR_Set_level