RTEMS CPU Kit with SuperCore
4.11.2
mnt
data0
chrisj
rtems
releases
rtems-release.git
4.11.2
ws-rtems
rtems-4.11.2
cpukit
score
cpu
bfin
rtems
bfin
bfin.h
Go to the documentation of this file.
1
10
/*
11
* COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
12
* modified by Alain Schaefer <alain.schaefer@easc.ch>
13
* and Antonio Giovanini <antonio@atos.com.br>
14
*
15
* The license and distribution terms for this file may be
16
* found in the file LICENSE in this distribution or at
17
* http://www.rtems.org/license/LICENSE.
18
*
19
*/
20
21
#ifndef _RTEMS_BFIN_BFIN_H
22
#define _RTEMS_BFIN_BFIN_H
23
24
#ifdef __cplusplus
25
extern
"C"
{
26
#endif
27
28
/* Scratchpad SRAM */
29
30
#define SCRATCH 0xFFB00000
31
#define SCRATCH_SIZE 0x1000
32
#define SCRATCH_TOP 0xFFB00ffc
33
34
35
/* System Interrupt Controller Chapter 4*/
36
#define SIC_RVECT 0xFFC00108
37
#define SIC_IMASK 0xFFC0010C
38
#define SIC_IAR0 0xFFC00110
39
#define SIC_IAR1 0xFFC00114
40
#define SIC_IAR2 0xFFC00118
41
#define SIC_ISR 0xFFC00120
42
#define SIC_IWR 0xFFC00124
43
44
/* Event Vector Table Chapter 4 */
45
46
#define EVT0 0xFFE02000
47
#define EVT1 0xFFE02004
48
#define EVT2 0xFFE02008
49
#define EVT3 0xFFE0200C
50
#define EVT4 0xFFE02010
51
#define EVT5 0xFFE02014
52
#define EVT6 0xFFE02018
53
#define EVT7 0xFFE0201C
54
#define EVT8 0xFFE02020
55
#define EVT9 0xFFE02024
56
#define EVT10 0xFFE02028
57
#define EVT11 0xFFE0202C
58
#define EVT12 0xFFE02030
59
#define EVT13 0xFFE02034
60
#define EVT14 0xFFE02038
61
#define EVT15 0xFFE0203C
62
#define IMASK 0xFFE02104
63
#define IPEND 0xFFE02108
64
#define ILAT 0xFFE0210C
65
#define IPRIO 0xFFE02110
66
67
68
#define TCNTL 0xFFE03000
69
#define TPERIOD 0xFFE03004
70
#define TSCALE 0xFFE03008
71
#define TCOUNT 0xFFE0300C
72
73
/* Masks for Timer Control */
74
#define TMPWR 0x00000001
75
#define TMREN 0x00000002
76
#define TAUTORLD 0x00000004
77
#define TINT 0x00000008
78
79
/* Event Bit Positions */
80
#define EVT_IVTMR_P 0x00000006
81
82
#define EVT_IVTMR (1 << EVT_IVTMR_P)
83
84
#ifdef __cplusplus
85
}
86
#endif
87
88
#endif
/* _RTEMS_SCORE_BFIN_H */
Generated by
1.8.13