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cpuimpl.h
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1 
7 /*
8  * Copyright (c) 2018.
9  * Amaan Cheval <amaan.cheval@gmail.com>
10  *
11  * Copyright (c) 2013, 2016 embedded brains GmbH
12  *
13  * The license and distribution terms for this file may be
14  * found in the file LICENSE in this distribution or at
15  * http://www.rtems.org/license/LICENSE.
16  */
17 
18 #ifndef _RTEMS_SCORE_CPUIMPL_H
19 #define _RTEMS_SCORE_CPUIMPL_H
20 
21 #include <rtems/score/cpu.h>
22 
33 #define CPU_PER_CPU_CONTROL_SIZE 0
34 
35 #ifndef ASM
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
42 {
43  /* TODO */
44 }
45 
47 {
48  __asm__ volatile ( ".word 0" );
49 }
50 
51 RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
52 {
53  while (1) {
54  /* TODO */
55  }
56 }
57 
59 {
60  __asm__ volatile ( "nop" );
61 }
62 
63 #ifdef __cplusplus
64 }
65 #endif
66 
67 #endif /* !ASM */
68 
71 #endif /* _RTEMS_SCORE_CPUIMPL_H */
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation(void)
Emits a no operation instruction (nop).
Definition: cpuimpl.h:132
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal(void)
Emits an illegal instruction.
Definition: cpuimpl.h:122