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apic.h
1 /*
2  * Copyright (c) 2018.
3  * Amaan Cheval <amaan.cheval@gmail.com>
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #ifndef _AMD64_APIC_H
28 #define _AMD64_APIC_H
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
34 /* The address of the MSR pointing to the APIC base physical address */
35 #define APIC_BASE_MSR 0x1B
36 /* Value to hardware-enable the APIC through the APIC_BASE_MSR */
37 #define APIC_BASE_MSR_ENABLE 0x800
38 
39 /*
40  * Since amd64_apic_base is an array of 32-bit elements, these byte-offsets
41  * need to be divided by 4 to index the array.
42  */
43 #define APIC_OFFSET(val) (val >> 2)
44 
45 #define APIC_REGISTER_APICID APIC_OFFSET(0x20)
46 #define APIC_REGISTER_EOI APIC_OFFSET(0x0B0)
47 #define APIC_REGISTER_SPURIOUS APIC_OFFSET(0x0F0)
48 #define APIC_REGISTER_LVT_TIMER APIC_OFFSET(0x320)
49 #define APIC_REGISTER_TIMER_INITCNT APIC_OFFSET(0x380)
50 #define APIC_REGISTER_TIMER_CURRCNT APIC_OFFSET(0x390)
51 #define APIC_REGISTER_TIMER_DIV APIC_OFFSET(0x3E0)
52 
53 #define APIC_DISABLE 0x10000
54 #define APIC_EOI_ACK 0
55 #define APIC_SELECT_TMR_PERIODIC 0x20000
56 #define APIC_SPURIOUS_ENABLE 0x100
57 
58 #ifdef __cplusplus
59 }
60 #endif
61 
62 #endif /* _AMD64_APIC_H */