RTEMS  5.0.0
pcireg.h
1 /* $NetBSD: pcireg.h,v 1.44 2003/12/02 16:31:06 briggs Exp $ */
2 
3 /*
4  * Copyright (c) 1995, 1996, 1999, 2000
5  * Christopher G. Demetriou. All rights reserved.
6  * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
7  * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  * notice, this list of conditions and the following disclaimer in the
16  * documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  * must display the following acknowledgement:
19  * This product includes software developed by Charles M. Hannum.
20  * 4. The name of the author may not be used to endorse or promote products
21  * derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 #include <bsp.h>
35 
36 /*
37  * PCI Class and Revision Register; defines type and revision of device.
38  */
39 #define PCI_CLASS_REG 0x08
40 
41 #define PCI_CLASS_SHIFT 24
42 #define PCI_CLASS_MASK 0xff
43 #define PCI_CLASS(cr) \
44  (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
45 
46 #define PCI_SUBCLASS_SHIFT 16
47 #define PCI_SUBCLASS_MASK 0xff
48 #define PCI_SUBCLASS(cr) \
49  (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
50 
51 #define PCI_INTERFACE_SHIFT 8
52 #define PCI_INTERFACE_MASK 0xff
53 #define PCI_INTERFACE(cr) \
54  (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
55 
56 #define PCI_REVISION_SHIFT 0
57 #define PCI_REVISION_MASK 0xff
58 #define PCI_REVISION(cr) \
59  (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
60 
61 #define PCI_CLASS_CODE(mainclass, subclass, interface) \
62  ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
63  (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
64  (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
65 
66 /* base classes */
67 #define PCI_CLASS_PREHISTORIC 0x00
68 #define PCI_CLASS_MASS_STORAGE 0x01
69 #define PCI_CLASS_NETWORK 0x02
70 #define PCI_CLASS_DISPLAY 0x03
71 #define PCI_CLASS_MULTIMEDIA 0x04
72 #define PCI_CLASS_MEMORY 0x05
73 #define PCI_CLASS_BRIDGE 0x06
74 #define PCI_CLASS_COMMUNICATIONS 0x07
75 #define PCI_CLASS_SYSTEM 0x08
76 #define PCI_CLASS_INPUT 0x09
77 #define PCI_CLASS_DOCK 0x0a
78 #define PCI_CLASS_PROCESSOR 0x0b
79 #define PCI_CLASS_SERIALBUS 0x0c
80 #define PCI_CLASS_WIRELESS 0x0d
81 #define PCI_CLASS_I2O 0x0e
82 #define PCI_CLASS_SATCOM 0x0f
83 #define PCI_CLASS_CRYPTO 0x10
84 #define PCI_CLASS_DASP 0x11
85 #define PCI_CLASS_UNDEFINED 0xff
86 
87 /* 0x00 prehistoric subclasses */
88 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
89 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
90 
91 /* 0x01 mass storage subclasses */
92 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
93 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
94 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
95 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
96 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
97 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05
98 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06
99 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
100 
101 /* 0x02 network subclasses */
102 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
103 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
104 #define PCI_SUBCLASS_NETWORK_FDDI 0x02
105 #define PCI_SUBCLASS_NETWORK_ATM 0x03
106 #define PCI_SUBCLASS_NETWORK_ISDN 0x04
107 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
108 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
109 #define PCI_SUBCLASS_NETWORK_MISC 0x80
110 
111 /* 0x03 display subclasses */
112 #define PCI_SUBCLASS_DISPLAY_VGA 0x00
113 #define PCI_SUBCLASS_DISPLAY_XGA 0x01
114 #define PCI_SUBCLASS_DISPLAY_3D 0x02
115 #define PCI_SUBCLASS_DISPLAY_MISC 0x80
116 
117 /* 0x04 multimedia subclasses */
118 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
119 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
120 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02
121 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
122 
123 /* 0x05 memory subclasses */
124 #define PCI_SUBCLASS_MEMORY_RAM 0x00
125 #define PCI_SUBCLASS_MEMORY_FLASH 0x01
126 #define PCI_SUBCLASS_MEMORY_MISC 0x80
127 
128 /* 0x06 bridge subclasses */
129 #define PCI_SUBCLASS_BRIDGE_HOST 0x00
130 #define PCI_SUBCLASS_BRIDGE_ISA 0x01
131 #define PCI_SUBCLASS_BRIDGE_EISA 0x02
132 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */
133 #define PCI_SUBCLASS_BRIDGE_PCI 0x04
134 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
135 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
136 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
137 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
138 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09
139 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
140 #define PCI_SUBCLASS_BRIDGE_MISC 0x80
141 
142 /* 0x07 communications subclasses */
143 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
144 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
145 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02
146 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
147 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04
148 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05
149 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
150 
151 /* 0x08 system subclasses */
152 #define PCI_SUBCLASS_SYSTEM_PIC 0x00
153 #define PCI_SUBCLASS_SYSTEM_DMA 0x01
154 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02
155 #define PCI_SUBCLASS_SYSTEM_RTC 0x03
156 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04
157 #define PCI_SUBCLASS_SYSTEM_MISC 0x80
158 
159 /* 0x09 input subclasses */
160 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
161 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
162 #define PCI_SUBCLASS_INPUT_MOUSE 0x02
163 #define PCI_SUBCLASS_INPUT_SCANNER 0x03
164 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
165 #define PCI_SUBCLASS_INPUT_MISC 0x80
166 
167 /* 0x0a dock subclasses */
168 #define PCI_SUBCLASS_DOCK_GENERIC 0x00
169 #define PCI_SUBCLASS_DOCK_MISC 0x80
170 
171 /* 0x0b processor subclasses */
172 #define PCI_SUBCLASS_PROCESSOR_386 0x00
173 #define PCI_SUBCLASS_PROCESSOR_486 0x01
174 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
175 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
176 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
177 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
178 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
179 
180 /* 0x0c serial bus subclasses */
181 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
182 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
183 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02
184 #define PCI_SUBCLASS_SERIALBUS_USB 0x03
185 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */
186 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05
187 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06
188 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
189 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
190 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
191 
192 /* 0x0d wireless subclasses */
193 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00
194 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01
195 #define PCI_SUBCLASS_WIRELESS_RF 0x10
196 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11
197 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
198 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20
199 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21
200 #define PCI_SUBCLASS_WIRELESS_MISC 0x80
201 
202 /* 0x0e I2O (Intelligent I/O) subclasses */
203 #define PCI_SUBCLASS_I2O_STANDARD 0x00
204 
205 /* 0x0f satellite communication subclasses */
206 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */
207 #define PCI_SUBCLASS_SATCOM_TV 0x01
208 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02
209 #define PCI_SUBCLASS_SATCOM_VOICE 0x03
210 #define PCI_SUBCLASS_SATCOM_DATA 0x04
211 
212 /* 0x10 encryption/decryption subclasses */
213 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00
214 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10
215 #define PCI_SUBCLASS_CRYPTO_MISC 0x80
216 
217 /* 0x11 data acquisition and signal processing subclasses */
218 #define PCI_SUBCLASS_DASP_DPIO 0x00
219 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01
220 #define PCI_SUBCLASS_DASP_SYNC 0x10
221 #define PCI_SUBCLASS_DASP_MGMT 0x20
222 #define PCI_SUBCLASS_DASP_MISC 0x80
223 
224 /*
225  * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
226  */
227 #define PCI_BHLC_REG 0x0c
228 
229 #define PCI_BIST_SHIFT 24
230 #define PCI_BIST_MASK 0xff
231 #define PCI_BIST(bhlcr) \
232  (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
233 
234 #define PCI_HDRTYPE_SHIFT 16
235 #define PCI_HDRTYPE_MASK 0xff
236 #define PCI_HDRTYPE(bhlcr) \
237  (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
238 
239 #define PCI_HDRTYPE_TYPE(bhlcr) \
240  (PCI_HDRTYPE(bhlcr) & 0x7f)
241 #define PCI_HDRTYPE_MULTIFN(bhlcr) \
242  ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
243 
244 #define PCI_LATTIMER_SHIFT 8
245 #define PCI_LATTIMER_MASK 0xff
246 #define PCI_LATTIMER(bhlcr) \
247  (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
248 
249 #define PCI_CACHELINE_SHIFT 0
250 #define PCI_CACHELINE_MASK 0xff
251 #define PCI_CACHELINE(bhlcr) \
252  (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
253 
254 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \
255  ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \
256  (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \
257  (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \
258  (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \
259  (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
260 
261 /*
262  * PCI header type
263  */
264 #define PCI_HDRTYPE_DEVICE 0
265 #define PCI_HDRTYPE_PPB 1
266 #define PCI_HDRTYPE_PCB 2
267 
268 /*
269  * Mapping registers
270  */
271 #define PCI_MAPREG_START 0x10
272 #define PCI_MAPREG_END 0x28
273 #define PCI_MAPREG_ROM 0x30
274 #define PCI_MAPREG_PPB_END 0x18
275 #define PCI_MAPREG_PCB_END 0x14
276 
277 #define PCI_MAPREG_TYPE(mr) \
278  ((mr) & PCI_MAPREG_TYPE_MASK)
279 #define PCI_MAPREG_TYPE_MASK 0x00000001
280 
281 #define PCI_MAPREG_TYPE_MEM 0x00000000
282 #define PCI_MAPREG_TYPE_IO 0x00000001
283 #define PCI_MAPREG_ROM_ENABLE 0x00000001
284 
285 #define PCI_MAPREG_MEM_TYPE(mr) \
286  ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
287 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
288 
289 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
290 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
291 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
292 
293 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \
294  (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
295 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
296 
297 #define PCI_MAPREG_MEM_ADDR(mr) \
298  ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
299 #define PCI_MAPREG_MEM_SIZE(mr) \
300  (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
301 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
302 
303 #define PCI_MAPREG_MEM64_ADDR(mr) \
304  ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
305 #define PCI_MAPREG_MEM64_SIZE(mr) \
306  (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
307 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL
308 
309 #define PCI_MAPREG_IO_ADDR(mr) \
310  ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK)
311 #define PCI_MAPREG_IO_SIZE(mr) \
312  (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
313 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
314 
315 #define PCI_MAPREG_SIZE_TO_MASK(size) \
316  (-(size))
317 
318 #define PCI_MAPREG_NUM(offset) \
319  (((unsigned)(offset)-PCI_MAPREG_START)/4)
320 
321 
322 /*
323  * Cardbus CIS pointer (PCI rev. 2.1)
324  */
325 #define PCI_CARDBUS_CIS_REG 0x28
326 
327 /*
328  * Subsystem identification register; contains a vendor ID and a device ID.
329  * Types/macros for PCI_ID_REG apply.
330  * (PCI rev. 2.1)
331  */
332 #define PCI_SUBSYS_ID_REG 0x2c
333 
334 /*
335  * capabilities link list (PCI rev. 2.2)
336  */
337 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
338 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
339 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
340 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
341 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
342 
343 #define PCI_CAP_RESERVED0 0x00
344 #define PCI_CAP_PWRMGMT 0x01
345 #define PCI_CAP_AGP 0x02
346 #define PCI_CAP_VPD 0x03
347 #define PCI_CAP_SLOTID 0x04
348 #define PCI_CAP_MSI 0x05
349 #define PCI_CAP_CPCI_HOTSWAP 0x06
350 #define PCI_CAP_PCIX 0x07
351 #define PCI_CAP_LDT 0x08
352 #define PCI_CAP_VENDSPEC 0x09
353 #define PCI_CAP_DEBUGPORT 0x0a
354 #define PCI_CAP_CPCI_RSRCCTL 0x0b
355 #define PCI_CAP_HOTPLUG 0x0c
356 #define PCI_CAP_AGP8 0x0e
357 #define PCI_CAP_SECURE 0x0f
358 #define PCI_CAP_PCIEXPRESS 0x10
359 #define PCI_CAP_MSIX 0x11
360 
361 /*
362  * Vital Product Data; access via capability pointer (PCI rev 2.2).
363  */
364 #define PCI_VPD_ADDRESS_MASK 0x7fff
365 #define PCI_VPD_ADDRESS_SHIFT 16
366 #define PCI_VPD_ADDRESS(ofs) \
367  (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT)
368 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4)
369 #define PCI_VPD_OPFLAG 0x80000000
370 
371 /*
372  * Power Management Capability; access via capability pointer.
373  */
374 
375 /* Power Management Capability Register */
376 #define PCI_PMCR 0x02
377 #define PCI_PMCR_D1SUPP 0x0200
378 #define PCI_PMCR_D2SUPP 0x0400
379 /* Power Management Control Status Register */
380 #define PCI_PMCSR 0x04
381 #define PCI_PMCSR_STATE_MASK 0x03
382 #define PCI_PMCSR_STATE_D0 0x00
383 #define PCI_PMCSR_STATE_D1 0x01
384 #define PCI_PMCSR_STATE_D2 0x02
385 #define PCI_PMCSR_STATE_D3 0x03
386 
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