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irq.h
1 /*
2  * irq.h
3  *
4  * This include file describe the data structure and the functions implemented
5  * by rtems to write interrupt handlers.
6  *
7  *
8  * MPC5xx port sponsored by Defence Research and Development Canada - Suffield
9  * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
10  *
11  * Derived from libbsp/powerpc/mbx8xx/irq/irq.h:
12  *
13  * CopyRight (C) 1999 valette@crf.canon.fr
14  *
15  * This code is heavilly inspired by the public specification of STREAM V2
16  * that can be found at :
17  *
18  * <http://www.chorus.com/Documentation/index.html> by following
19  * the STREAM API Specification Document link.
20  *
21  * The license and distribution terms for this file may be
22  * found in the file LICENSE in this distribution or at
23  * http://www.rtems.org/license/LICENSE.
24  */
25 
26 #ifndef _LIBCPU_IRQ_H
27 #define _LIBCPU_IRQ_H
28 
29 #include <rtems/irq.h>
30 
31 #define CPU_ASM_IRQ_VECTOR_BASE 0x0
32 
33 #ifndef ASM
34 
35 extern volatile unsigned int ppc_cached_irq_mask;
36 
37 /*
38  * Symblolic IRQ names and related definitions.
39  */
40 
41  /*
42  * Base vector for our USIU IRQ handlers.
43  */
44 #define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE)
45  /*
46  * USIU IRQ handler related definitions
47  */
48 #define CPU_USIU_IRQ_COUNT (16) /* 16 reserved but in the future... */
49 #define CPU_USIU_IRQ_MIN_OFFSET (0)
50 #define CPU_USIU_IRQ_MAX_OFFSET (CPU_USIU_IRQ_MIN_OFFSET + CPU_USIU_IRQ_COUNT - 1)
51  /*
52  * UIMB IRQ handlers related definitions
53  */
54 #define CPU_UIMB_IRQ_COUNT (32 - 8) /* first 8 overlap USIU */
55 #define CPU_UIMB_IRQ_MIN_OFFSET (CPU_USIU_IRQ_COUNT + CPU_USIU_VECTOR_BASE)
56 #define CPU_UIMB_IRQ_MAX_OFFSET (CPU_UIMB_IRQ_MIN_OFFSET + CPU_UIMB_IRQ_COUNT - 1)
57  /*
58  * PowerPc exceptions handled as interrupt where a rtems managed interrupt
59  * handler might be connected
60  */
61 #define CPU_PROC_IRQ_COUNT (1)
62 #define CPU_PROC_IRQ_MIN_OFFSET (CPU_UIMB_IRQ_MAX_OFFSET + 1)
63 #define CPU_PROC_IRQ_MAX_OFFSET (CPU_PROC_IRQ_MIN_OFFSET + CPU_PROC_IRQ_COUNT - 1)
64  /*
65  * Summary
66  */
67 #define CPU_IRQ_COUNT (CPU_PROC_IRQ_MAX_OFFSET + 1)
68 #define CPU_MIN_OFFSET (CPU_USIU_IRQ_MIN_OFFSET)
69 #define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET)
70  /*
71  * USIU IRQ symbolic name definitions.
72  */
73 #define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0)
74 #define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1)
75 
76 #define CPU_USIU_EXT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 2)
77 #define CPU_USIU_INT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 3)
78 
79 #define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4)
80 #define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5)
81 
82 #define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6)
83 #define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7)
84 
85 #define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8)
86 #define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9)
87 
88 #define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10)
89 #define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11)
90 
91 #define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12)
92 #define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13)
93 
94 #define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14)
95 #define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15)
96 
97  /*
98  * Symbolic names for UISU interrupt sources.
99  */
100 #define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6)
101 #define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7)
102 
103  /*
104  * UIMB IRQ symbolic name definitions. The first 8 sources are aliases to
105  * the USIU interrupts of the same number, because they are detected in
106  * the USIU pending register rather than the UIMB pending register.
107  */
108 #define CPU_UIMB_IRQ_0 (CPU_USIU_INT_IRQ_0)
109 #define CPU_UIMB_IRQ_1 (CPU_USIU_INT_IRQ_1)
110 #define CPU_UIMB_IRQ_2 (CPU_USIU_INT_IRQ_2)
111 #define CPU_UIMB_IRQ_3 (CPU_USIU_INT_IRQ_3)
112 #define CPU_UIMB_IRQ_4 (CPU_USIU_INT_IRQ_4)
113 #define CPU_UIMB_IRQ_5 (CPU_USIU_INT_IRQ_5)
114 #define CPU_UIMB_IRQ_6 (CPU_USIU_INT_IRQ_6)
115 #define CPU_UIMB_IRQ_7 (CPU_USIU_INT_IRQ_7)
116 
117 #define CPU_UIMB_IRQ_8 (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
118 #define CPU_UIMB_IRQ_9 (CPU_UIMB_IRQ_MIN_OFFSET+ 1)
119 #define CPU_UIMB_IRQ_10 (CPU_UIMB_IRQ_MIN_OFFSET+ 2)
120 #define CPU_UIMB_IRQ_11 (CPU_UIMB_IRQ_MIN_OFFSET+ 3)
121 #define CPU_UIMB_IRQ_12 (CPU_UIMB_IRQ_MIN_OFFSET+ 4)
122 #define CPU_UIMB_IRQ_13 (CPU_UIMB_IRQ_MIN_OFFSET+ 5)
123 #define CPU_UIMB_IRQ_14 (CPU_UIMB_IRQ_MIN_OFFSET+ 6)
124 #define CPU_UIMB_IRQ_15 (CPU_UIMB_IRQ_MIN_OFFSET+ 7)
125 #define CPU_UIMB_IRQ_16 (CPU_UIMB_IRQ_MIN_OFFSET+ 8)
126 #define CPU_UIMB_IRQ_17 (CPU_UIMB_IRQ_MIN_OFFSET+ 9)
127 #define CPU_UIMB_IRQ_18 (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
128 #define CPU_UIMB_IRQ_19 (CPU_UIMB_IRQ_MIN_OFFSET+11)
129 #define CPU_UIMB_IRQ_20 (CPU_UIMB_IRQ_MIN_OFFSET+12)
130 #define CPU_UIMB_IRQ_21 (CPU_UIMB_IRQ_MIN_OFFSET+13)
131 #define CPU_UIMB_IRQ_22 (CPU_UIMB_IRQ_MIN_OFFSET+14)
132 #define CPU_UIMB_IRQ_23 (CPU_UIMB_IRQ_MIN_OFFSET+15)
133 #define CPU_UIMB_IRQ_24 (CPU_UIMB_IRQ_MIN_OFFSET+16)
134 #define CPU_UIMB_IRQ_25 (CPU_UIMB_IRQ_MIN_OFFSET+17)
135 #define CPU_UIMB_IRQ_26 (CPU_UIMB_IRQ_MIN_OFFSET+18)
136 #define CPU_UIMB_IRQ_27 (CPU_UIMB_IRQ_MIN_OFFSET+19)
137 #define CPU_UIMB_IRQ_28 (CPU_UIMB_IRQ_MIN_OFFSET+20)
138 #define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21)
139 #define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22)
140 #define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23)
141 
142  /*
143  * Symbolic names for UIMB interrupt sources.
144  */
145 #define CPU_IRQ_SCI (CPU_UIMB_IRQ_5)
146 
147  /*
148  * Processor exceptions handled as rtems IRQ symbolic name definitions.
149  */
150 #define CPU_DECREMENTER (CPU_PROC_IRQ_MIN_OFFSET)
151 
152 /*
153  * Convert an rtems_irq_number constant to an interrupt level
154  * suitable for programming into an I/O device's interrupt level field.
155  */
156 int CPU_irq_level_from_symbolic_name(const rtems_irq_number name);
157 
158 /*-------------------------------------------------------------------------+
159 | Function Prototypes.
160 +--------------------------------------------------------------------------*/
161 
162 extern void CPU_rtems_irq_mng_init(unsigned cpuId);
163 
164 typedef struct MPC5XX_Interrupt_frame {
165  uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */
166  uint32_t calleeLr; /* link register used by callees: SVR4/EABI */
167 
168  /* This is what is left out of the primary contexts */
169  uint32_t gpr0;
170  uint32_t gpr2; /* play safe */
171  uint32_t gpr3;
172  uint32_t gpr4;
173  uint32_t gpr5;
174  uint32_t gpr6;
175  uint32_t gpr7;
176  uint32_t gpr8;
177  uint32_t gpr9;
178  uint32_t gpr10;
179  uint32_t gpr11;
180  uint32_t gpr12;
181  uint32_t gpr13; /* Play safe */
182  uint32_t gpr28; /* For internal use by the IRQ handler */
183  uint32_t gpr29; /* For internal use by the IRQ handler */
184  uint32_t gpr30; /* For internal use by the IRQ handler */
185  uint32_t gpr31; /* For internal use by the IRQ handler */
186  uint32_t cr; /* Bits of this are volatile, so no-one may save */
187  uint32_t ctr;
188  uint32_t xer;
189  uint32_t lr;
190  uint32_t pc;
191  uint32_t msr;
192  uint32_t pad[3];
193 } MPC5XX_Interrupt_frame;
194 
195 void C_dispatch_irq_handler(MPC5XX_Interrupt_frame *frame, unsigned int excNum);
196 
197 #endif
198 
199 #endif
MPC5XX_Interrupt_frame
Definition: irq.h:164
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