RTEMS  5.0.0
tx4938.h
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1 
7 /*
8  * COPYRIGHT (c) 1989-2012.
9  * On-Line Applications Research Corporation (OAR).
10  *
11  * The license and distribution terms for this file may be
12  * found in the file LICENSE in this distribution or at
13  * http://www.rtems.org/license/LICENSE.
14  */
15 
16 #ifndef __TX4938_h
17 #define __TX4938_h
18 
19 #define TX4938_REG_BASE 0xFF1F0000
20 
21 /* PCI1 Registers */
22 #define TX4938_PCI1_PCIID 0x7000
23 #define TX4938_PCI1_PCISTATUS 0x7004
24 #define TX4938_PCI1_PCICFG1 0x700c
25 #define TX4938_PCI1_P2GM1PLBASE 0x7018
26 #define TX4938_PCI1_P2GCFG 0x7090
27 #define TX4938_PCI1_PBAREQPORT 0x7100
28 #define TX4938_PCI1_PBACFG 0x7104
29 #define TX4938_PCI1_G2PM0GBASE 0x7120
30 #define TX4938_PCI1_G2PIOGBASE 0x7138
31 #define TX4938_PCI1_G2PM0MASK 0x7140
32 #define TX4938_PCI1_G2PIOMASK 0x714c
33 #define TX4938_PCI1_G2PM0PBASE 0x7150
34 #define TX4938_PCI1_G2PIOPBASE 0x7168
35 #define TX4938_PCI1_PCICCFG 0x7170
36 #define TX4938_PCI1_PCICSTATUS 0x7174
37 #define TX4938_PCI1_P2GM1GBASE 0x7188
38 #define TX4938_PCI1_G2PCFGADRS 0x71a0
39 #define TX4938_PCI1_G2PCFGDATA 0x71a4
40 
41 /*
42  * Configuration Registers
43  */
44 #define TX4938_CFG_CCFG 0xE000 /* Chip Configuration Register */
45 #define TX4938_CFG_REVID 0xE008 /* Chip Revision ID Register */
46 #define TX4938_CFG_PCFG 0xE010 /* Pin Configuration Register */
47 #define TX4938_CFG_TOEA 0xE018 /* TimeOut Error Access Address Register */
48 #define TX4938_CFG_CLKCTR 0xE020 /* Clock Control Register */
49 #define TX4938_CFG_GARBC 0xE030 /* GBUS Arbiter Control Register */
50 #define TX4938_CFG_RAMP 0xE048 /* Register Address Mapping Register */
51 
52 /* Pin Configuration register bits */
53 #define SELCHI 0x00100000
54 #define SELTMR0 0x00000200
55 
56 
57 /*
58  * Timer Registers
59  */
60 
61 #define TX4938_TIMER0_BASE 0xF000
62 #define TX4938_TIMER1_BASE 0xF100
63 #define TX4938_TIMER2_BASE 0xF200
64 
65 #define TX4938_TIMER_TCR 0x00 /* Timer Control Register */
66 #define TX4938_TIMER_TISR 0x04 /* Timer Interrupt Status Register */
67 #define TX4938_TIMER_CPRA 0x08 /* Compare Register A */
68 #define TX4938_TIMER_CPRB 0x0C /* Compare Register B */
69 #define TX4938_TIMER_ITMR 0x10 /* Interval Timer Mode Register */
70 #define TX4938_TIMER_CCDR 0x20 /* Divide Cycle Register */
71 #define TX4938_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */
72 #define TX4938_TIMER_WTMR 0x40 /* Reserved Register */
73 #define TX4938_TIMER_TRR 0xF0 /* Timer Read Register */
74 
75 /* ITMR register bits */
76 #define TIMER_CLEAR_ENABLE_MASK 0x1
77 #define TIMER_INT_ENABLE_MASK 0x8000
78 
79 /* PGMR register bits */
80 #define FFI 0x1
81 #define TPIAE 0x4000
82 #define TPIBE 0x8000
83 
84 /* TISR register bits */
85 #define TIIS 0x1
86 #define TPIAS 0x2
87 #define TPIBS 0x4
88 #define TWIS 0x8
89 
90 
91 /*
92  * Interrupt Controller Registers
93  */
94 #define TX4938_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */
95 #define TX4938_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */
96 #define TX4938_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */
97 #define TX4938_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */
98 #define TX4938_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */
99 #define TX4938_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */
100 #define TX4938_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */
101 #define TX4938_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */
102 #define TX4938_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */
103 #define TX4938_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */
104 #define TX4938_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */
105 #define TX4938_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */
106 #define TX4938_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */
107 #define TX4938_IRQCTL_PND 0xF680 /* Interrupt Pending Register */
108 #define TX4938_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */
109 #define TX4938_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */
110 #define TX4938_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */
111 #define TX4938_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */
112 #define TX4938_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */
113 #define TX4938_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */
114 #define TX4938_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */
115 
116 #define TX4938_REG_READ( _base, _register ) \
117  *((volatile uint32_t *)((_base) + (_register)))
118 
119 #define TX4938_REG_WRITE( _base, _register, _value ) \
120  *((volatile uint32_t *)((_base) + (_register))) = (_value)
121 
122 /************************************************************************
123  * TX49 Register field encodings
124 *************************************************************************/
125 /******** reg: CCFG ********/
126 /* field: PCIDIVMODE */
127 #define TX4938_CCFG_SYSSP_SHF 6
128 #define TX4938_CCFG_SYSSP_MSK (MSK(2) << TX4938_CCFG_SYSSP_SHF)
129 
130 /* field: PCI1DMD */
131 #define TX4938_CCFG_PCI1DMD_SHF 8
132 #define TX4938_CCFG_PCI1DMD_MSK (MSK(1) << TX4938_CCFG_PCI1DMD_SHF)
133 
134 /* field: PCIDIVMODE */
135 #define TX4938_CCFG_PCIDIVMODE_SHF 10
136 #define TX4938_CCFG_PCIDIVMODE_MSK (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF)
137 
138 /* field: PCI1-66 */
139 #define TX4938_CCFG_PCI166_SHF 21
140 #define TX4938_CCFG_PCI166_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF)
141 
142 /* field: PCIMODE */
143 #define TX4938_CCFG_PCIMODE_SHF 22
144 #define TX4938_CCFG_PCIMODE_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF)
145 
146 /* field: BRDTY */
147 #define TX4938_CCFG_BRDTY_SHF 36
148 #define TX4938_CCFG_RRDTY_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF)
149 
150 /* field: BRDRV */
151 #define TX4938_CCFG_BRDRV_SHF 32
152 #define TX4938_CCFG_BRDRV_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF)
153 
154 /******** reg: CLKCTR ********/
155 /* field: PCIC1RST */
156 #define TX4938_CLKCTR_PCIC1RST_SHF 11
157 #define TX4938_CLKCTR_PCIC1RST_MSK (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF)
158 
159 /******** reg: PCISTATUS ********/
160 /* field: MEMSP */
161 #define TX4938_PCI_PCISTATUS_MEMSP_SHF 1
162 #define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF)
163 
164 /* field: BM */
165 #define TX4938_PCI_PCISTATUS_BM_SHF 2
166 #define TX4938_PCI_PCISTATUS_BM_MSK (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF)
167 
168 /******** reg: PBACFG ********/
169 /* field: RPBA */
170 #define TX4938_PCI_PBACFG_RPBA_SHF 2
171 #define TX4938_PCI_PBACFG_RPBA_MSK (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF)
172 
173 /* field: PBAEN */
174 #define TX4938_PCI_PBACFG_PBAEN_SHF 1
175 #define TX4938_PCI_PBACFG_PBAEN_MSK (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF)
176 
177 /******** reg: PCICFG ********/
178 /* field: G2PM0EN */
179 #define TX4938_PCI_PCICFG_G2PM0EN_SHF 6
180 #define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF)
181 
182 /* field: G2PIOEN */
183 #define TX4938_PCI_PCICFG_G2PIOEN_SHF 5
184 #define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF)
185 
186 /* field: TCAR */
187 #define TX4938_PCI_PCICFG_TCAR_SHF 4
188 #define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF)
189 
190 
191 #endif
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