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#define | SSE_TEST_IRQ 10 |
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#define | MXCSR_FZ (1<<15) /* Flush to zero */ |
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#define | MXCSR_RC(x) (((x)&3)<<13) /* Rounding ctrl */ |
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#define | MXCSR_PM (1<<12) /* Precision msk */ |
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#define | MXCSR_UM (1<<11) /* Underflow msk */ |
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#define | MXCSR_OM (1<<10) /* Overflow msk */ |
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#define | MXCSR_ZM (1<< 9) /* Divbyzero msk */ |
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#define | MXCSR_DM (1<< 8) /* Denormal msk */ |
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#define | MXCSR_IM (1<< 7) /* Invalidop msk */ |
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#define | MXCSR_DAZ (1<< 6) /* Denorml are 0 */ |
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#define | MXCSR_PE (1<< 5) /* Precision flg */ |
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#define | MXCSR_UE (1<< 4) /* Underflow flg */ |
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#define | MXCSR_OE (1<< 3) /* Overflow flg */ |
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#define | MXCSR_ZE (1<< 2) /* Divbyzero flg */ |
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#define | MXCSR_DE (1<< 1) /* Denormal flg */ |
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#define | MXCSR_IE (1<< 0) /* Invalidop flg */ |
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#define | MXCSR_ALLM (MXCSR_PM | MXCSR_UM | MXCSR_OM | MXCSR_ZM | MXCSR_DM | MXCSR_IM) |
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#define | MXCSR_ALLE (MXCSR_PE | MXCSR_UE | MXCSR_OE | MXCSR_ZE | MXCSR_DE | MXCSR_IE) |
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#define | FPSR_B (1<<15) /* FPU busy */ |
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#define | FPSR_C3 (1<<14) /* Cond code C3 */ |
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#define | FPSR_TOP(x) (((x)&7)<<11) /* TOP */ |
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#define | FPSR_C2 (1<<10) /* Cond code C2 */ |
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#define | FPSR_C1 (1<< 9) /* Cond code C1 */ |
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#define | FPSR_C0 (1<< 8) /* Cond code C0 */ |
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#define | FPSR_ES (1<< 7) /* Error summary */ |
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#define | FPSR_SF (1<< 6) /* Stack fault */ |
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#define | FPSR_PE (1<< 5) /* Precision flg */ |
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#define | FPSR_UE (1<< 4) /* Underflow flg */ |
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#define | FPSR_OE (1<< 3) /* Overflow flg */ |
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#define | FPSR_ZE (1<< 2) /* Divbyzero flg */ |
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#define | FPSR_DE (1<< 1) /* Denormal flg */ |
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#define | FPSR_IE (1<< 0) /* Invalidop flg */ |
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#define | FPCW_X (1<<12) /* Infinity ctrl */ |
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#define | FPCW_RC(x) (((x)&3)<<10) /* Rounding ctrl */ |
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#define | FPCW_PC(x) (((x)&3)<< 8) /* Precision ctl */ |
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#define | FPCW_PM (1<< 5) /* Precision msk */ |
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#define | FPCW_UM (1<< 4) /* Underflow msk */ |
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#define | FPCW_OM (1<< 3) /* Overflow msk */ |
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#define | FPCW_ZM (1<< 2) /* Divbyzero msk */ |
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#define | FPCW_DM (1<< 1) /* Denormal msk */ |
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#define | FPCW_IM (1<< 0) /* Invalidop msk */ |
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#define | FPCW_ALLM (FPCW_PM | FPCW_UM | FPCW_OM | FPCW_ZM | FPCW_DM | FPCW_IM) |
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#define | FPSR_ALLE (FPSR_ES | FPSR_SF | FPSR_PE | FPSR_UE | FPSR_OE | FPSR_ZE | FPSR_DE | FPSR_IE) |
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#define | FPUCLOBBER |
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#define | SSECLOBBER |
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#define | H08 "0x%02"PRIx8 |
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#define | H16 "0x%04"PRIx16 |
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#define | H32 "0x%08"PRIx32 |
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#define | F16 "mismatch ("H16" != "H16")\n" |
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#define | FLDCMP(fld, fmt) |
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#define | FLTCMP(i) |
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#define | XMMCMP(i) |
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#define | FP_EXC 0 |
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#define | IRQ_EXC 1 |
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#define | SSE_EXC -1 |
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#define | __INTRAISE(x) " int $32+"#x" \n" |
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#define | INTRAISE(x) __INTRAISE(x) |
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#define | SSE_TEST_HP_FAILED 1 |
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#define | SSE_TEST_FSPR_FAILED 2 |
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#define | SSE_TEST_CTXTCMP_FAILED 4 |
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#define | MKCASE(X) case FPE_##X: msg="FPE_"#X; break; |
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#define | CLRXMM(i) __asm__ volatile("pxor %%xmm"#i", %%xmm"#i:::"xmm"#i) |
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struct Context_Control_sse | __attribute__ ((aligned(16))) |
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void | fp_st1 (uint8_t(*p_dst)[10], double v) |
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void | fp_st (Context_Control_sse *p_ctxt, int i, double v) |
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double | fp_ld1 (uint8_t(*p_src)[10]) |
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double | fp_ld (Context_Control_sse *p_ctxt, int i) |
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void | all_clobber (uint32_t v1, uint32_t v2) |
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| __asm__ ("all_clobber: \ " finit \" " movq 0(%esp), %xmm0 \" " punpcklqdq %xmm0, %xmm0 \" " movdqa %xmm0, %xmm1 \" " movdqa %xmm0, %xmm2 \" " movdqa %xmm0, %xmm3 \" " movdqa %xmm0, %xmm4 \" " movdqa %xmm0, %xmm5 \" " movdqa %xmm0, %xmm6 \" " movdqa %xmm0, %xmm7 \" " ret \") |
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void | init_ctxt (Context_Control_sse *p_ctxt) |
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| __asm__ ("init_ctxt: \ " finit \" " mov 4(%esp), %eax\" " fxsave(%eax) \" " fwait \" " ret \") |
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| __asm__ ("do_raise: \ " fwait \" " test %eax, %eax \" " je 2f \" " jl 1f \" " jmp 2f \" "1:sqrtps %xmm0, %xmm0 \" "2: \" " ret \") |
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int | main (int argc, char **argv) |
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uint32_t | mfcr4 () |
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void | mtcr4 (uint32_t rval) |
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uint32_t | mfmxcsr () |
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void | mtmxcsr (uint32_t rval) |
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float | sseraise () |
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Test FPU/SSE Context Save and Restore.