39 #ifndef __ALTERA_ALT_I2C_H__ 40 #define __ALTERA_ALT_I2C_H__ 97 #define ALT_I2C_CON_MST_MOD_E_DIS 0x0 103 #define ALT_I2C_CON_MST_MOD_E_EN 0x1 106 #define ALT_I2C_CON_MST_MOD_LSB 0 108 #define ALT_I2C_CON_MST_MOD_MSB 0 110 #define ALT_I2C_CON_MST_MOD_WIDTH 1 112 #define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 114 #define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe 116 #define ALT_I2C_CON_MST_MOD_RESET 0x1 118 #define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0) 120 #define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001) 145 #define ALT_I2C_CON_SPEED_E_STANDARD 0x1 151 #define ALT_I2C_CON_SPEED_E_FAST 0x2 154 #define ALT_I2C_CON_SPEED_LSB 1 156 #define ALT_I2C_CON_SPEED_MSB 2 158 #define ALT_I2C_CON_SPEED_WIDTH 2 160 #define ALT_I2C_CON_SPEED_SET_MSK 0x00000006 162 #define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 164 #define ALT_I2C_CON_SPEED_RESET 0x2 166 #define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1) 168 #define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006) 193 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 199 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 202 #define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 204 #define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 206 #define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 208 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 210 #define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 212 #define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 214 #define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3) 216 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008) 239 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 245 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 248 #define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 250 #define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 252 #define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 254 #define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 256 #define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef 258 #define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 260 #define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4) 262 #define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010) 304 #define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 310 #define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 313 #define ALT_I2C_CON_IC_RESTART_EN_LSB 5 315 #define ALT_I2C_CON_IC_RESTART_EN_MSB 5 317 #define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 319 #define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 321 #define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf 323 #define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 325 #define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5) 327 #define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020) 353 #define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 359 #define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 362 #define ALT_I2C_CON_IC_SLV_DIS_LSB 6 364 #define ALT_I2C_CON_IC_SLV_DIS_MSB 6 366 #define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 368 #define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 370 #define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf 372 #define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 374 #define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6) 376 #define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040) 391 uint32_t master_mode : 1;
393 uint32_t ic_10bitaddr_slave : 1;
394 uint32_t ic_10bitaddr_master : 1;
395 uint32_t ic_restart_en : 1;
396 uint32_t ic_slave_disable : 1;
405 #define ALT_I2C_CON_OFST 0x0 407 #define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) 447 #define ALT_I2C_TAR_IC_TAR_LSB 0 449 #define ALT_I2C_TAR_IC_TAR_MSB 9 451 #define ALT_I2C_TAR_IC_TAR_WIDTH 10 453 #define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff 455 #define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00 457 #define ALT_I2C_TAR_IC_TAR_RESET 0x55 459 #define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0) 461 #define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff) 488 #define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0 494 #define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1 497 #define ALT_I2C_TAR_GC_OR_START_LSB 10 499 #define ALT_I2C_TAR_GC_OR_START_MSB 10 501 #define ALT_I2C_TAR_GC_OR_START_WIDTH 1 503 #define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400 505 #define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff 507 #define ALT_I2C_TAR_GC_OR_START_RESET 0x0 509 #define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10) 511 #define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400) 536 #define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0 542 #define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1 545 #define ALT_I2C_TAR_SPECIAL_LSB 11 547 #define ALT_I2C_TAR_SPECIAL_MSB 11 549 #define ALT_I2C_TAR_SPECIAL_WIDTH 1 551 #define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800 553 #define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff 555 #define ALT_I2C_TAR_SPECIAL_RESET 0x0 557 #define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11) 559 #define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800) 582 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0 588 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1 591 #define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12 593 #define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12 595 #define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1 597 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000 599 #define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff 601 #define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1 603 #define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12) 605 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000) 620 uint32_t ic_tar : 10;
621 uint32_t gc_or_start : 1;
622 uint32_t special : 1;
623 uint32_t ic_10bitaddr_master : 1;
632 #define ALT_I2C_TAR_OFST 0x4 634 #define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST)) 669 #define ALT_I2C_SAR_IC_SAR_LSB 0 671 #define ALT_I2C_SAR_IC_SAR_MSB 9 673 #define ALT_I2C_SAR_IC_SAR_WIDTH 10 675 #define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff 677 #define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00 679 #define ALT_I2C_SAR_IC_SAR_RESET 0x55 681 #define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0) 683 #define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff) 698 uint32_t ic_sar : 10;
707 #define ALT_I2C_SAR_OFST 0x8 709 #define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST)) 740 #define ALT_I2C_DATA_CMD_DAT_LSB 0 742 #define ALT_I2C_DATA_CMD_DAT_MSB 7 744 #define ALT_I2C_DATA_CMD_DAT_WIDTH 8 746 #define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff 748 #define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 750 #define ALT_I2C_DATA_CMD_DAT_RESET 0x0 752 #define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0) 754 #define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff) 791 #define ALT_I2C_DATA_CMD_CMD_E_RD 0x1 797 #define ALT_I2C_DATA_CMD_CMD_E_WR 0x0 800 #define ALT_I2C_DATA_CMD_CMD_LSB 8 802 #define ALT_I2C_DATA_CMD_CMD_MSB 8 804 #define ALT_I2C_DATA_CMD_CMD_WIDTH 1 806 #define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 808 #define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff 810 #define ALT_I2C_DATA_CMD_CMD_RESET 0x0 812 #define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8) 814 #define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100) 846 #define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 852 #define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 855 #define ALT_I2C_DATA_CMD_STOP_LSB 9 857 #define ALT_I2C_DATA_CMD_STOP_MSB 9 859 #define ALT_I2C_DATA_CMD_STOP_WIDTH 1 861 #define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 863 #define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff 865 #define ALT_I2C_DATA_CMD_STOP_RESET 0x0 867 #define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9) 869 #define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200) 899 #define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 905 #define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 908 #define ALT_I2C_DATA_CMD_RESTART_LSB 10 910 #define ALT_I2C_DATA_CMD_RESTART_MSB 10 912 #define ALT_I2C_DATA_CMD_RESTART_WIDTH 1 914 #define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 916 #define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff 918 #define ALT_I2C_DATA_CMD_RESTART_RESET 0x0 920 #define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10) 922 #define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400) 940 uint32_t restart : 1;
949 #define ALT_I2C_DATA_CMD_OFST 0x10 951 #define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) 985 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 987 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 989 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16 991 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff 993 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000 995 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190 997 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) 999 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) 1001 #ifndef __ASSEMBLY__ 1014 uint32_t ic_ss_scl_hcnt : 16;
1023 #define ALT_I2C_SS_SCL_HCNT_OFST 0x14 1025 #define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST)) 1055 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 1057 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 1059 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16 1061 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff 1063 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000 1065 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6 1067 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) 1069 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) 1071 #ifndef __ASSEMBLY__ 1084 uint32_t ic_ss_scl_lcnt : 16;
1093 #define ALT_I2C_SS_SCL_LCNT_OFST 0x18 1095 #define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST)) 1127 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 1129 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 1131 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16 1133 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff 1135 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000 1137 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c 1139 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) 1141 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) 1143 #ifndef __ASSEMBLY__ 1156 uint32_t ic_fs_scl_hcnt : 16;
1165 #define ALT_I2C_FS_SCL_HCNT_OFST 0x1c 1167 #define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST)) 1197 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 1199 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 1201 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16 1203 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff 1205 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000 1207 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82 1209 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) 1211 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) 1213 #ifndef __ASSEMBLY__ 1226 uint32_t ic_fs_scl_lcnt : 16;
1235 #define ALT_I2C_FS_SCL_LCNT_OFST 0x20 1237 #define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST)) 1278 #define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 1280 #define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 1282 #define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 1284 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 1286 #define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe 1288 #define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 1290 #define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) 1292 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) 1307 #define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 1309 #define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 1311 #define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 1313 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 1315 #define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd 1317 #define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 1319 #define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) 1321 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002) 1337 #define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 1339 #define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 1341 #define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 1343 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 1345 #define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb 1347 #define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 1349 #define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) 1351 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004) 1365 #define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 1367 #define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 1369 #define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 1371 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 1373 #define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 1375 #define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 1377 #define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) 1379 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008) 1395 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 1397 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 1399 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 1401 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 1403 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef 1405 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 1407 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) 1409 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) 1426 #define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 1428 #define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 1430 #define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 1432 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 1434 #define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf 1436 #define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 1438 #define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) 1440 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020) 1460 #define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 1462 #define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 1464 #define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 1466 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 1468 #define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf 1470 #define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 1472 #define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) 1474 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) 1487 #define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 1489 #define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 1491 #define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 1493 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 1495 #define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f 1497 #define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 1499 #define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) 1501 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080) 1525 #define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 1527 #define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 1529 #define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 1531 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 1533 #define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff 1535 #define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 1537 #define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) 1539 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) 1551 #define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 1553 #define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 1555 #define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 1557 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 1559 #define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff 1561 #define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 1563 #define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) 1565 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200) 1577 #define ALT_I2C_INTR_STAT_R_START_DET_LSB 10 1579 #define ALT_I2C_INTR_STAT_R_START_DET_MSB 10 1581 #define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 1583 #define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 1585 #define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff 1587 #define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 1589 #define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10) 1591 #define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400) 1605 #define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 1607 #define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 1609 #define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 1611 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 1613 #define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff 1615 #define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 1617 #define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) 1619 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) 1621 #ifndef __ASSEMBLY__ 1634 const uint32_t r_rx_under : 1;
1635 const uint32_t r_rx_over : 1;
1636 const uint32_t r_rx_full : 1;
1637 const uint32_t r_tx_over : 1;
1638 const uint32_t r_tx_empty : 1;
1639 const uint32_t r_rd_req : 1;
1640 const uint32_t r_tx_abrt : 1;
1641 const uint32_t r_rx_done : 1;
1642 const uint32_t r_activity : 1;
1643 const uint32_t r_stop_det : 1;
1644 const uint32_t r_start_det : 1;
1645 const uint32_t r_gen_call : 1;
1654 #define ALT_I2C_INTR_STAT_OFST 0x2c 1656 #define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) 1694 #define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0 1696 #define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0 1698 #define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1 1700 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001 1702 #define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe 1704 #define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1 1706 #define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) 1708 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) 1723 #define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1 1725 #define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1 1727 #define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1 1729 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002 1731 #define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd 1733 #define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1 1735 #define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) 1737 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002) 1753 #define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2 1755 #define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2 1757 #define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1 1759 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004 1761 #define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb 1763 #define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1 1765 #define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) 1767 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004) 1781 #define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3 1783 #define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3 1785 #define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1 1787 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008 1789 #define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7 1791 #define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1 1793 #define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) 1795 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008) 1812 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4 1814 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4 1816 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1 1818 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010 1820 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef 1822 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1 1824 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) 1826 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) 1843 #define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5 1845 #define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5 1847 #define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1 1849 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020 1851 #define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf 1853 #define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1 1855 #define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) 1857 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020) 1877 #define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6 1879 #define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6 1881 #define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1 1883 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040 1885 #define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf 1887 #define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1 1889 #define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) 1891 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) 1904 #define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7 1906 #define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7 1908 #define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1 1910 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080 1912 #define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f 1914 #define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1 1916 #define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) 1918 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080) 1942 #define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8 1944 #define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8 1946 #define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1 1948 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100 1950 #define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff 1952 #define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0 1954 #define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) 1956 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) 1968 #define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9 1970 #define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9 1972 #define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1 1974 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200 1976 #define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff 1978 #define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0 1980 #define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) 1982 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200) 1994 #define ALT_I2C_INTR_MSK_M_START_DET_LSB 10 1996 #define ALT_I2C_INTR_MSK_M_START_DET_MSB 10 1998 #define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1 2000 #define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400 2002 #define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff 2004 #define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0 2006 #define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10) 2008 #define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400) 2022 #define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11 2024 #define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11 2026 #define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1 2028 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800 2030 #define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff 2032 #define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1 2034 #define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) 2036 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) 2038 #ifndef __ASSEMBLY__ 2051 uint32_t m_rx_under : 1;
2052 uint32_t m_rx_over : 1;
2053 uint32_t m_rx_full : 1;
2054 uint32_t m_tx_over : 1;
2055 uint32_t m_tx_empty : 1;
2056 uint32_t m_rd_req : 1;
2057 uint32_t m_tx_abrt : 1;
2058 uint32_t m_rx_done : 1;
2059 uint32_t m_activity : 1;
2060 uint32_t m_stop_det : 1;
2061 uint32_t m_start_det : 1;
2062 uint32_t m_gen_call : 1;
2071 #define ALT_I2C_INTR_MSK_OFST 0x30 2073 #define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST)) 2112 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0 2114 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0 2116 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1 2118 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001 2120 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe 2122 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0 2124 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) 2126 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) 2141 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1 2143 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1 2145 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1 2147 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002 2149 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd 2151 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0 2153 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) 2155 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002) 2171 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2 2173 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2 2175 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1 2177 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004 2179 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb 2181 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0 2183 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) 2185 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004) 2199 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3 2201 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3 2203 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1 2205 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008 2207 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7 2209 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0 2211 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) 2213 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008) 2230 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4 2232 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4 2234 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 2236 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010 2238 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef 2240 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 2242 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) 2244 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) 2261 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5 2263 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5 2265 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1 2267 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020 2269 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf 2271 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0 2273 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) 2275 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020) 2295 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6 2297 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6 2299 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1 2301 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040 2303 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf 2305 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0 2307 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) 2309 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) 2322 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7 2324 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7 2326 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1 2328 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080 2330 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f 2332 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0 2334 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) 2336 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080) 2360 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8 2362 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8 2364 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1 2366 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100 2368 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff 2370 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0 2372 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) 2374 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) 2386 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9 2388 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9 2390 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1 2392 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200 2394 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff 2396 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0 2398 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) 2400 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200) 2412 #define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10 2414 #define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10 2416 #define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1 2418 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400 2420 #define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff 2422 #define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0 2424 #define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10) 2426 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400) 2440 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11 2442 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11 2444 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1 2446 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800 2448 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff 2450 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0 2452 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) 2454 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) 2456 #ifndef __ASSEMBLY__ 2469 const uint32_t rx_under : 1;
2470 const uint32_t rx_over : 1;
2471 const uint32_t rx_full : 1;
2472 const uint32_t tx_over : 1;
2473 const uint32_t tx_empty : 1;
2474 const uint32_t rd_req : 1;
2475 const uint32_t tx_abrt : 1;
2476 const uint32_t rx_done : 1;
2477 const uint32_t activity : 1;
2478 const uint32_t stop_det : 1;
2479 const uint32_t start_det : 1;
2480 const uint32_t gen_call : 1;
2489 #define ALT_I2C_RAW_INTR_STAT_OFST 0x34 2491 #define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST)) 2520 #define ALT_I2C_RX_TL_RX_TL_LSB 0 2522 #define ALT_I2C_RX_TL_RX_TL_MSB 7 2524 #define ALT_I2C_RX_TL_RX_TL_WIDTH 8 2526 #define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff 2528 #define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00 2530 #define ALT_I2C_RX_TL_RX_TL_RESET 0x0 2532 #define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0) 2534 #define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff) 2536 #ifndef __ASSEMBLY__ 2558 #define ALT_I2C_RX_TL_OFST 0x38 2560 #define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST)) 2589 #define ALT_I2C_TX_TL_TX_TL_LSB 0 2591 #define ALT_I2C_TX_TL_TX_TL_MSB 7 2593 #define ALT_I2C_TX_TL_TX_TL_WIDTH 8 2595 #define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff 2597 #define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00 2599 #define ALT_I2C_TX_TL_TX_TL_RESET 0x0 2601 #define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0) 2603 #define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff) 2605 #ifndef __ASSEMBLY__ 2627 #define ALT_I2C_TX_TL_OFST 0x3c 2629 #define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST)) 2656 #define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0 2658 #define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0 2660 #define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1 2662 #define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001 2664 #define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe 2666 #define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0 2668 #define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0) 2670 #define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001) 2672 #ifndef __ASSEMBLY__ 2685 const uint32_t clr_intr : 1;
2694 #define ALT_I2C_CLR_INTR_OFST 0x40 2696 #define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST)) 2721 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 2723 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 2725 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1 2727 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001 2729 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe 2731 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 2733 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) 2735 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) 2737 #ifndef __ASSEMBLY__ 2750 const uint32_t clr_rx_under : 1;
2759 #define ALT_I2C_CLR_RX_UNDER_OFST 0x44 2761 #define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST)) 2786 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0 2788 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0 2790 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1 2792 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001 2794 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe 2796 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 2798 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0) 2800 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001) 2802 #ifndef __ASSEMBLY__ 2815 const uint32_t clr_rx_over : 1;
2824 #define ALT_I2C_CLR_RX_OVER_OFST 0x48 2826 #define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST)) 2851 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0 2853 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0 2855 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1 2857 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001 2859 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe 2861 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 2863 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0) 2865 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001) 2867 #ifndef __ASSEMBLY__ 2880 const uint32_t clr_tx_over : 1;
2889 #define ALT_I2C_CLR_TX_OVER_OFST 0x4c 2891 #define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST)) 2916 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0 2918 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0 2920 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1 2922 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001 2924 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe 2926 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 2928 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0) 2930 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001) 2932 #ifndef __ASSEMBLY__ 2945 const uint32_t clr_rd_req : 1;
2954 #define ALT_I2C_CLR_RD_REQ_OFST 0x50 2956 #define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST)) 2984 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0 2986 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0 2988 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1 2990 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001 2992 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe 2994 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0 2996 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0) 2998 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001) 3000 #ifndef __ASSEMBLY__ 3013 const uint32_t clr_tx_abort : 1;
3022 #define ALT_I2C_CLR_TX_ABRT_OFST 0x54 3024 #define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST)) 3049 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0 3051 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0 3053 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1 3055 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001 3057 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe 3059 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 3061 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0) 3063 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001) 3065 #ifndef __ASSEMBLY__ 3078 const uint32_t clr_rx_done : 1;
3087 #define ALT_I2C_CLR_RX_DONE_OFST 0x58 3089 #define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST)) 3118 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 3120 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 3122 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1 3124 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001 3126 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe 3128 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 3130 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) 3132 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) 3134 #ifndef __ASSEMBLY__ 3147 const uint32_t clr_activity : 1;
3156 #define ALT_I2C_CLR_ACTIVITY_OFST 0x5c 3158 #define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST)) 3183 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0 3185 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0 3187 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1 3189 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001 3191 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe 3193 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 3195 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0) 3197 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001) 3199 #ifndef __ASSEMBLY__ 3212 const uint32_t clr_stop_det : 1;
3221 #define ALT_I2C_CLR_STOP_DET_OFST 0x60 3223 #define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST)) 3248 #define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0 3250 #define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0 3252 #define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1 3254 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001 3256 #define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe 3258 #define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0 3260 #define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0) 3262 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001) 3264 #ifndef __ASSEMBLY__ 3277 const uint32_t clr_start_det : 1;
3286 #define ALT_I2C_CLR_START_DET_OFST 0x64 3288 #define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST)) 3313 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 3315 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 3317 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1 3319 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001 3321 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe 3323 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 3325 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) 3327 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) 3329 #ifndef __ASSEMBLY__ 3342 const uint32_t clr_gen_call : 1;
3351 #define ALT_I2C_CLR_GEN_CALL_OFST 0x68 3353 #define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST)) 3423 #define ALT_I2C_EN_EN_E_DIS 0x0 3429 #define ALT_I2C_EN_EN_E_EN 0x1 3432 #define ALT_I2C_EN_EN_LSB 0 3434 #define ALT_I2C_EN_EN_MSB 0 3436 #define ALT_I2C_EN_EN_WIDTH 1 3438 #define ALT_I2C_EN_EN_SET_MSK 0x00000001 3440 #define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe 3442 #define ALT_I2C_EN_EN_RESET 0x0 3444 #define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0) 3446 #define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001) 3457 #define ALT_I2C_EN_TXABT_LSB 1 3459 #define ALT_I2C_EN_TXABT_MSB 1 3461 #define ALT_I2C_EN_TXABT_WIDTH 1 3463 #define ALT_I2C_EN_TXABT_SET_MSK 0x00000002 3465 #define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd 3467 #define ALT_I2C_EN_TXABT_RESET 0x0 3469 #define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1) 3471 #define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002) 3473 #ifndef __ASSEMBLY__ 3486 uint32_t enable : 1;
3487 uint32_t txabort : 1;
3496 #define ALT_I2C_EN_OFST 0x6c 3498 #define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST)) 3539 #define ALT_I2C_STAT_ACTIVITY_LSB 0 3541 #define ALT_I2C_STAT_ACTIVITY_MSB 0 3543 #define ALT_I2C_STAT_ACTIVITY_WIDTH 1 3545 #define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001 3547 #define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe 3549 #define ALT_I2C_STAT_ACTIVITY_RESET 0x0 3551 #define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) 3553 #define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) 3575 #define ALT_I2C_STAT_TFNF_E_FULL 0x0 3581 #define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1 3584 #define ALT_I2C_STAT_TFNF_LSB 1 3586 #define ALT_I2C_STAT_TFNF_MSB 1 3588 #define ALT_I2C_STAT_TFNF_WIDTH 1 3590 #define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002 3592 #define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd 3594 #define ALT_I2C_STAT_TFNF_RESET 0x1 3596 #define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1) 3598 #define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002) 3620 #define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0 3626 #define ALT_I2C_STAT_TFE_E_EMPTY 0x1 3629 #define ALT_I2C_STAT_TFE_LSB 2 3631 #define ALT_I2C_STAT_TFE_MSB 2 3633 #define ALT_I2C_STAT_TFE_WIDTH 1 3635 #define ALT_I2C_STAT_TFE_SET_MSK 0x00000004 3637 #define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb 3639 #define ALT_I2C_STAT_TFE_RESET 0x1 3641 #define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2) 3643 #define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004) 3665 #define ALT_I2C_STAT_RFNE_E_EMPTY 0x0 3671 #define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1 3674 #define ALT_I2C_STAT_RFNE_LSB 3 3676 #define ALT_I2C_STAT_RFNE_MSB 3 3678 #define ALT_I2C_STAT_RFNE_WIDTH 1 3680 #define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008 3682 #define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7 3684 #define ALT_I2C_STAT_RFNE_RESET 0x0 3686 #define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3) 3688 #define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008) 3710 #define ALT_I2C_STAT_RFF_E_NOTFULL 0x0 3716 #define ALT_I2C_STAT_RFF_E_FULL 0x1 3719 #define ALT_I2C_STAT_RFF_LSB 4 3721 #define ALT_I2C_STAT_RFF_MSB 4 3723 #define ALT_I2C_STAT_RFF_WIDTH 1 3725 #define ALT_I2C_STAT_RFF_SET_MSK 0x00000010 3727 #define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef 3729 #define ALT_I2C_STAT_RFF_RESET 0x0 3731 #define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4) 3733 #define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010) 3759 #define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0 3765 #define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1 3768 #define ALT_I2C_STAT_MST_ACTIVITY_LSB 5 3770 #define ALT_I2C_STAT_MST_ACTIVITY_MSB 5 3772 #define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1 3774 #define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020 3776 #define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf 3778 #define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0 3780 #define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5) 3782 #define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020) 3807 #define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0 3813 #define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1 3816 #define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6 3818 #define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6 3820 #define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1 3822 #define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040 3824 #define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf 3826 #define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0 3828 #define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6) 3830 #define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040) 3832 #ifndef __ASSEMBLY__ 3845 const uint32_t activity : 1;
3846 const uint32_t tfnf : 1;
3847 const uint32_t tfe : 1;
3848 const uint32_t rfne : 1;
3849 const uint32_t rff : 1;
3850 const uint32_t mst_activity : 1;
3851 const uint32_t slv_activity : 1;
3860 #define ALT_I2C_STAT_OFST 0x70 3862 #define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST)) 3895 #define ALT_I2C_TXFLR_TXFLR_LSB 0 3897 #define ALT_I2C_TXFLR_TXFLR_MSB 6 3899 #define ALT_I2C_TXFLR_TXFLR_WIDTH 7 3901 #define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f 3903 #define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80 3905 #define ALT_I2C_TXFLR_TXFLR_RESET 0x0 3907 #define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0) 3909 #define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f) 3911 #ifndef __ASSEMBLY__ 3924 const uint32_t txflr : 7;
3933 #define ALT_I2C_TXFLR_OFST 0x74 3935 #define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST)) 3967 #define ALT_I2C_RXFLR_RXFLR_LSB 0 3969 #define ALT_I2C_RXFLR_RXFLR_MSB 6 3971 #define ALT_I2C_RXFLR_RXFLR_WIDTH 7 3973 #define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f 3975 #define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80 3977 #define ALT_I2C_RXFLR_RXFLR_RESET 0x0 3979 #define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0) 3981 #define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f) 3983 #ifndef __ASSEMBLY__ 3996 const uint32_t rxflr : 7;
4005 #define ALT_I2C_RXFLR_OFST 0x78 4007 #define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST)) 4034 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0 4036 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15 4038 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16 4040 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff 4042 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000 4044 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1 4046 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0) 4048 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff) 4050 #ifndef __ASSEMBLY__ 4063 uint32_t ic_sda_hold : 16;
4072 #define ALT_I2C_SDA_HOLD_OFST 0x7c 4074 #define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST)) 4122 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0 4124 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0 4126 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1 4128 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001 4130 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe 4132 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0 4134 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0) 4136 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001) 4148 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1 4150 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1 4152 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1 4154 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002 4156 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd 4158 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0 4160 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1) 4162 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002) 4175 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2 4177 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2 4179 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1 4181 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004 4183 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb 4185 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0 4187 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2) 4189 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004) 4202 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3 4204 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3 4206 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1 4208 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008 4210 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7 4212 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0 4214 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3) 4216 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008) 4228 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4 4230 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4 4232 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1 4234 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010 4236 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef 4238 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0 4240 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4) 4242 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010) 4255 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5 4257 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5 4259 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1 4261 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020 4263 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf 4265 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0 4267 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5) 4269 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020) 4281 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6 4283 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6 4285 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1 4287 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040 4289 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf 4291 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0 4293 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6) 4295 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040) 4307 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7 4309 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7 4311 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1 4313 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080 4315 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f 4317 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0 4319 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7) 4321 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080) 4334 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8 4336 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8 4338 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1 4340 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100 4342 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff 4344 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0 4346 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8) 4348 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100) 4367 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9 4369 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9 4371 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1 4373 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200 4375 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff 4377 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0 4379 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9) 4381 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200) 4393 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10 4395 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10 4397 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1 4399 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400 4401 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff 4403 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0 4405 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10) 4407 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400) 4419 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11 4421 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11 4423 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1 4425 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800 4427 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff 4429 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0 4431 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11) 4433 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800) 4446 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12 4448 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12 4450 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1 4452 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000 4454 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff 4456 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0 4458 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12) 4460 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000) 4473 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13 4475 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13 4477 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1 4479 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000 4481 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff 4483 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 4485 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13) 4487 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000) 4503 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14 4505 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14 4507 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1 4509 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000 4511 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff 4513 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0 4515 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14) 4517 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000) 4530 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15 4532 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15 4534 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1 4536 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000 4538 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff 4540 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0 4542 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15) 4544 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000) 4546 #ifndef __ASSEMBLY__ 4559 uint32_t abrt_7b_addr_noack : 1;
4560 uint32_t abrt_10addr1_noack : 1;
4561 uint32_t abrt_10addr2_noack : 1;
4562 uint32_t abrt_txdata_noack : 1;
4563 uint32_t abrt_gcall_noack : 1;
4564 uint32_t abrt_gcall_read : 1;
4565 uint32_t abrt_hs_ackdet : 1;
4566 uint32_t abrt_sbyte_ackdet : 1;
4567 uint32_t abrt_hs_norstrt : 1;
4568 uint32_t abrt_sbyte_norstrt : 1;
4569 uint32_t abrt_10b_rd_norstrt : 1;
4570 uint32_t abrt_master_dis : 1;
4571 uint32_t arb_lost : 1;
4572 uint32_t abrt_slvflush_txfifo : 1;
4573 uint32_t abrt_slv_arblost : 1;
4574 uint32_t abrt_slvrd_intx : 1;
4583 #define ALT_I2C_TX_ABRT_SRC_OFST 0x80 4585 #define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST)) 4621 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1 4627 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0 4630 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0 4632 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0 4634 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1 4636 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001 4638 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe 4640 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 4642 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0) 4644 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001) 4646 #ifndef __ASSEMBLY__ 4668 #define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84 4670 #define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST)) 4708 #define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 4714 #define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 4717 #define ALT_I2C_DMA_CR_RDMAE_LSB 0 4719 #define ALT_I2C_DMA_CR_RDMAE_MSB 0 4721 #define ALT_I2C_DMA_CR_RDMAE_WIDTH 1 4723 #define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 4725 #define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe 4727 #define ALT_I2C_DMA_CR_RDMAE_RESET 0x0 4729 #define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) 4731 #define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001) 4753 #define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 4759 #define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 4762 #define ALT_I2C_DMA_CR_TDMAE_LSB 1 4764 #define ALT_I2C_DMA_CR_TDMAE_MSB 1 4766 #define ALT_I2C_DMA_CR_TDMAE_WIDTH 1 4768 #define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 4770 #define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd 4772 #define ALT_I2C_DMA_CR_TDMAE_RESET 0x0 4774 #define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) 4776 #define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002) 4778 #ifndef __ASSEMBLY__ 4801 #define ALT_I2C_DMA_CR_OFST 0x88 4803 #define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) 4830 #define ALT_I2C_DMA_TDLR_DMATDL_LSB 0 4832 #define ALT_I2C_DMA_TDLR_DMATDL_MSB 5 4834 #define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6 4836 #define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f 4838 #define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0 4840 #define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0 4842 #define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0) 4844 #define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f) 4846 #ifndef __ASSEMBLY__ 4859 uint32_t dmatdl : 6;
4868 #define ALT_I2C_DMA_TDLR_OFST 0x8c 4870 #define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST)) 4899 #define ALT_I2C_DMA_RDLR_DMARDL_LSB 0 4901 #define ALT_I2C_DMA_RDLR_DMARDL_MSB 5 4903 #define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 4905 #define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f 4907 #define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 4909 #define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 4911 #define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0) 4913 #define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f) 4915 #ifndef __ASSEMBLY__ 4928 uint32_t dmardl : 6;
4937 #define ALT_I2C_DMA_RDLR_OFST 0x90 4939 #define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) 4974 #define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0 4976 #define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7 4978 #define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8 4980 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff 4982 #define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00 4984 #define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64 4986 #define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0) 4988 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff) 4990 #ifndef __ASSEMBLY__ 5003 uint32_t sda_setup : 8;
5012 #define ALT_I2C_SDA_SETUP_OFST 0x94 5014 #define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST)) 5051 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0 5057 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1 5060 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 5062 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 5064 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1 5066 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001 5068 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe 5070 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 5072 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) 5074 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) 5076 #ifndef __ASSEMBLY__ 5089 uint32_t ack_gen_call : 1;
5098 #define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98 5100 #define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST)) 5136 #define ALT_I2C_EN_STAT_IC_EN_LSB 0 5138 #define ALT_I2C_EN_STAT_IC_EN_MSB 0 5140 #define ALT_I2C_EN_STAT_IC_EN_WIDTH 1 5142 #define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 5144 #define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe 5146 #define ALT_I2C_EN_STAT_IC_EN_RESET 0x0 5148 #define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0) 5150 #define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001) 5174 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 5176 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 5178 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 5180 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 5182 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd 5184 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 5186 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1) 5188 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002) 5209 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 5211 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 5213 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 5215 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 5217 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb 5219 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 5221 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2) 5223 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004) 5225 #ifndef __ASSEMBLY__ 5238 const uint32_t ic_en : 1;
5239 const uint32_t slv_disabled_while_busy : 1;
5240 const uint32_t slv_rx_data_lost : 1;
5249 #define ALT_I2C_EN_STAT_OFST 0x9c 5251 #define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) 5284 #define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0 5286 #define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7 5288 #define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8 5290 #define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff 5292 #define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00 5294 #define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2 5296 #define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0) 5298 #define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff) 5300 #ifndef __ASSEMBLY__ 5313 uint32_t spklen : 8;
5322 #define ALT_I2C_FS_SPKLEN_OFST 0xa0 5324 #define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST)) 5366 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 5369 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 5371 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 5373 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2 5375 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003 5377 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc 5379 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2 5381 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) 5383 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) 5404 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2 5407 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2 5409 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3 5411 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2 5413 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c 5415 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3 5417 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2 5419 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2) 5421 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c) 5442 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0 5445 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 5447 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 5449 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1 5451 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010 5453 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef 5455 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 5457 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4) 5459 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010) 5480 #define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1 5483 #define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5 5485 #define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5 5487 #define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1 5489 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020 5491 #define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf 5493 #define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1 5495 #define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5) 5497 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020) 5518 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1 5521 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6 5523 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6 5525 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1 5527 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040 5529 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf 5531 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1 5533 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6) 5535 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040) 5560 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 5563 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7 5565 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7 5567 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1 5569 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080 5571 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f 5573 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1 5575 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7) 5577 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080) 5598 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40 5601 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8 5603 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15 5605 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8 5607 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00 5609 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff 5611 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f 5613 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8) 5615 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00) 5636 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40 5639 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16 5641 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23 5643 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8 5645 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000 5647 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff 5649 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f 5651 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16) 5653 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000) 5655 #ifndef __ASSEMBLY__ 5668 const uint32_t apb_data_width : 2;
5669 const uint32_t max_speed_mode : 2;
5670 const uint32_t hc_count_values : 1;
5671 const uint32_t intr_io : 1;
5672 const uint32_t has_dma : 1;
5673 const uint32_t add_encoded_params : 1;
5674 const uint32_t rx_buffer_depth : 8;
5675 const uint32_t tx_buffer_depth : 8;
5684 #define ALT_I2C_COMP_PARAM_1_OFST 0xf4 5686 #define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST)) 5719 #define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a 5722 #define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0 5724 #define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31 5726 #define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32 5728 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff 5730 #define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000 5732 #define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a 5734 #define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0) 5736 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff) 5738 #ifndef __ASSEMBLY__ 5751 const uint32_t ic_comp_version : 32;
5759 #define ALT_I2C_COMP_VER_OFST 0xf8 5761 #define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST)) 5786 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0 5788 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31 5790 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32 5792 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff 5794 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000 5796 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 5798 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0) 5800 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff) 5802 #ifndef __ASSEMBLY__ 5815 const uint32_t ic_comp_type : 32;
5823 #define ALT_I2C_COMP_TYPE_OFST 0xfc 5825 #define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST)) 5827 #ifndef __ASSEMBLY__ 5840 volatile ALT_I2C_CON_t ic_con;
5841 volatile ALT_I2C_TAR_t ic_tar;
5842 volatile ALT_I2C_SAR_t ic_sar;
5843 volatile uint32_t _pad_0xc_0xf;
5844 volatile ALT_I2C_DATA_CMD_t ic_data_cmd;
5845 volatile ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt;
5846 volatile ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt;
5847 volatile ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt;
5848 volatile ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt;
5849 volatile uint32_t _pad_0x24_0x2b[2];
5850 volatile ALT_I2C_INTR_STAT_t ic_intr_stat;
5851 volatile ALT_I2C_INTR_MSK_t ic_intr_mask;
5852 volatile ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat;
5853 volatile ALT_I2C_RX_TL_t ic_rx_tl;
5854 volatile ALT_I2C_TX_TL_t ic_tx_tl;
5855 volatile ALT_I2C_CLR_INTR_t ic_clr_intr;
5856 volatile ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under;
5857 volatile ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over;
5858 volatile ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over;
5859 volatile ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req;
5860 volatile ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt;
5861 volatile ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done;
5862 volatile ALT_I2C_CLR_ACTIVITY_t ic_clr_activity;
5863 volatile ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det;
5864 volatile ALT_I2C_CLR_START_DET_t ic_clr_start_det;
5865 volatile ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call;
5866 volatile ALT_I2C_EN_t ic_enable;
5867 volatile ALT_I2C_STAT_t ic_status;
5868 volatile ALT_I2C_TXFLR_t ic_txflr;
5869 volatile ALT_I2C_RXFLR_t ic_rxflr;
5870 volatile ALT_I2C_SDA_HOLD_t ic_sda_hold;
5871 volatile ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source;
5872 volatile ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only;
5873 volatile ALT_I2C_DMA_CR_t ic_dma_cr;
5874 volatile ALT_I2C_DMA_TDLR_t ic_dma_tdlr;
5875 volatile ALT_I2C_DMA_RDLR_t ic_dma_rdlr;
5876 volatile ALT_I2C_SDA_SETUP_t ic_sda_setup;
5877 volatile ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call;
5878 volatile ALT_I2C_EN_STAT_t ic_enable_status;
5879 volatile ALT_I2C_FS_SPKLEN_t ic_fs_spklen;
5880 volatile uint32_t _pad_0xa4_0xf3[20];
5881 volatile ALT_I2C_COMP_PARAM_1_t ic_comp_param_1;
5882 volatile ALT_I2C_COMP_VER_t ic_comp_version;
5883 volatile ALT_I2C_COMP_TYPE_t ic_comp_type;
5887 typedef volatile struct ALT_I2C_s ALT_I2C_t;
5891 volatile uint32_t ic_con;
5892 volatile uint32_t ic_tar;
5893 volatile uint32_t ic_sar;
5894 volatile uint32_t _pad_0xc_0xf;
5895 volatile uint32_t ic_data_cmd;
5896 volatile uint32_t ic_ss_scl_hcnt;
5897 volatile uint32_t ic_ss_scl_lcnt;
5898 volatile uint32_t ic_fs_scl_hcnt;
5899 volatile uint32_t ic_fs_scl_lcnt;
5900 volatile uint32_t _pad_0x24_0x2b[2];
5901 volatile uint32_t ic_intr_stat;
5902 volatile uint32_t ic_intr_mask;
5903 volatile uint32_t ic_raw_intr_stat;
5904 volatile uint32_t ic_rx_tl;
5905 volatile uint32_t ic_tx_tl;
5906 volatile uint32_t ic_clr_intr;
5907 volatile uint32_t ic_clr_rx_under;
5908 volatile uint32_t ic_clr_rx_over;
5909 volatile uint32_t ic_clr_tx_over;
5910 volatile uint32_t ic_clr_rd_req;
5911 volatile uint32_t ic_clr_tx_abrt;
5912 volatile uint32_t ic_clr_rx_done;
5913 volatile uint32_t ic_clr_activity;
5914 volatile uint32_t ic_clr_stop_det;
5915 volatile uint32_t ic_clr_start_det;
5916 volatile uint32_t ic_clr_gen_call;
5917 volatile uint32_t ic_enable;
5918 volatile uint32_t ic_status;
5919 volatile uint32_t ic_txflr;
5920 volatile uint32_t ic_rxflr;
5921 volatile uint32_t ic_sda_hold;
5922 volatile uint32_t ic_tx_abrt_source;
5923 volatile uint32_t ic_slv_data_nack_only;
5924 volatile uint32_t ic_dma_cr;
5925 volatile uint32_t ic_dma_tdlr;
5926 volatile uint32_t ic_dma_rdlr;
5927 volatile uint32_t ic_sda_setup;
5928 volatile uint32_t ic_ack_general_call;
5929 volatile uint32_t ic_enable_status;
5930 volatile uint32_t ic_fs_spklen;
5931 volatile uint32_t _pad_0xa4_0xf3[20];
5932 volatile uint32_t ic_comp_param_1;
5933 volatile uint32_t ic_comp_version;
5934 volatile uint32_t ic_comp_type;
Definition: alt_i2c.h:935
Definition: alt_i2c.h:3994
Definition: alt_i2c.h:2878
Definition: alt_i2c.h:1012
Definition: alt_i2c.h:3340
Definition: alt_i2c.h:3076
Definition: alt_i2c.h:4789
Definition: alt_i2c.h:2813
Definition: alt_i2c.h:2616
Definition: alt_i2c.h:3011
Definition: alt_i2c.h:2547
Definition: alt_i2c.h:1224
Definition: alt_i2c.h:2943
Definition: alt_i2c.h:5749
Definition: alt_i2c.h:1154
Definition: alt_i2c.h:5311
Definition: alt_i2c.h:2748
Definition: alt_i2c.h:4557
Definition: alt_i2c.h:5813
Definition: alt_i2c.h:5087
Definition: alt_i2c.h:389
Definition: alt_i2c.h:2467
Definition: alt_i2c.h:696
Definition: alt_i2c.h:4926
Definition: alt_i2c.h:3145
Definition: alt_i2c.h:2683
Definition: alt_i2c.h:5889
Definition: alt_i2c.h:3275
Definition: alt_i2c.h:5236
Definition: alt_i2c.h:4061
Definition: alt_i2c.h:4857
Definition: alt_i2c.h:3484
Definition: alt_i2c.h:4657
Definition: alt_i2c.h:618
Definition: alt_i2c.h:1632
Definition: alt_i2c.h:2049
Definition: alt_i2c.h:5666
Definition: alt_i2c.h:3210
Definition: alt_i2c.h:5001
Definition: alt_i2c.h:3843
Definition: alt_i2c.h:3922
Definition: alt_i2c.h:5838
Definition: alt_i2c.h:1082