RTEMS  5.0.0
sdma.h
1 #ifndef __MGT5200_SDMA_H
2 #define __MGT5200_SDMA_H
3 
4 /******************************************************************************
5 *
6 * Copyright (c) 2004 Freescale Semiconductor, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included
16 * in all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 ******************************************************************************/
27 
28 typedef struct sdma_register_set {
29  volatile uint32 taskBar; /* MBAR_SDMA + 0x00 sdTpb */
30  volatile uint32 currentPointer; /* MBAR_SDMA + 0x04 sdMdeComplex */
31  volatile uint32 endPointer; /* MBAR_SDMA + 0x08 sdMdeComplex */
32  volatile uint32 variablePointer; /* MBAR_SDMA + 0x0c sdMdeComplex */
33 
34  volatile uint8 IntVect1; /* MBAR_SDMA + 0x10 sdPtd */
35  volatile uint8 IntVect2; /* MBAR_SDMA + 0x11 sdPtd */
36  volatile uint16 PtdCntrl; /* MBAR_SDMA + 0x12 sdPtd */
37 
38  volatile uint32 IntPend; /* MBAR_SDMA + 0x14 sdPtd */
39  volatile uint32 IntMask; /* MBAR_SDMA + 0x18 sdPtd */
40 
41  volatile uint32 TCR01; /* MBAR_SDMA + 0x1c sdPtd */
42  volatile uint32 TCR23; /* MBAR_SDMA + 0x20 sdPtd */
43  volatile uint32 TCR45; /* MBAR_SDMA + 0x24 sdPtd */
44  volatile uint32 TCR67; /* MBAR_SDMA + 0x28 sdPtd */
45  volatile uint32 TCR89; /* MBAR_SDMA + 0x2c sdPtd */
46  volatile uint32 TCRAB; /* MBAR_SDMA + 0x30 sdPtd */
47  volatile uint32 TCRCD; /* MBAR_SDMA + 0x34 sdPtd */
48  volatile uint32 TCREF; /* MBAR_SDMA + 0x38 sdPtd */
49 
50  volatile uint8 IPR0; /* MBAR_SDMA + 0x3c sdPtd */
51  volatile uint8 IPR1; /* MBAR_SDMA + 0x3d sdPtd */
52  volatile uint8 IPR2; /* MBAR_SDMA + 0x3e sdPtd */
53  volatile uint8 IPR3; /* MBAR_SDMA + 0x3f sdPtd */
54  volatile uint8 IPR4; /* MBAR_SDMA + 0x40 sdPtd */
55  volatile uint8 IPR5; /* MBAR_SDMA + 0x41 sdPtd */
56  volatile uint8 IPR6; /* MBAR_SDMA + 0x42 sdPtd */
57  volatile uint8 IPR7; /* MBAR_SDMA + 0x43 sdPtd */
58  volatile uint8 IPR8; /* MBAR_SDMA + 0x44 sdPtd */
59  volatile uint8 IPR9; /* MBAR_SDMA + 0x45 sdPtd */
60  volatile uint8 IPR10; /* MBAR_SDMA + 0x46 sdPtd */
61  volatile uint8 IPR11; /* MBAR_SDMA + 0x47 sdPtd */
62  volatile uint8 IPR12; /* MBAR_SDMA + 0x48 sdPtd */
63  volatile uint8 IPR13; /* MBAR_SDMA + 0x49 sdPtd */
64  volatile uint8 IPR14; /* MBAR_SDMA + 0x4a sdPtd */
65  volatile uint8 IPR15; /* MBAR_SDMA + 0x4b sdPtd */
66  volatile uint8 IPR16; /* MBAR_SDMA + 0x4c sdPtd */
67  volatile uint8 IPR17; /* MBAR_SDMA + 0x4d sdPtd */
68  volatile uint8 IPR18; /* MBAR_SDMA + 0x4e sdPtd */
69  volatile uint8 IPR19; /* MBAR_SDMA + 0x4f sdPtd */
70  volatile uint8 IPR20; /* MBAR_SDMA + 0x50 sdPtd */
71  volatile uint8 IPR21; /* MBAR_SDMA + 0x51 sdPtd */
72  volatile uint8 IPR22; /* MBAR_SDMA + 0x52 sdPtd */
73  volatile uint8 IPR23; /* MBAR_SDMA + 0x53 sdPtd */
74  volatile uint8 IPR24; /* MBAR_SDMA + 0x54 sdPtd */
75  volatile uint8 IPR25; /* MBAR_SDMA + 0x55 sdPtd */
76  volatile uint8 IPR26; /* MBAR_SDMA + 0x56 sdPtd */
77  volatile uint8 IPR27; /* MBAR_SDMA + 0x57 sdPtd */
78  volatile uint8 IPR28; /* MBAR_SDMA + 0x58 sdPtd */
79  volatile uint8 IPR29; /* MBAR_SDMA + 0x59 sdPtd */
80  volatile uint8 IPR30; /* MBAR_SDMA + 0x5a sdPtd */
81  volatile uint8 IPR31; /* MBAR_SDMA + 0x5b sdPtd */
82 
83  volatile uint32 cReqSelect; /* MBAR_SDMA + 0x5c sdPtd */
84  volatile uint32 taskSize0; /* MBAR_SDMA + 0x60 sdPtd */
85  volatile uint32 taskSize1; /* MBAR_SDMA + 0x64 sdPtd */
86  volatile uint32 MDEDebug; /* MBAR_SDMA + 0x68 sdMdeComplex */
87  volatile uint32 ADSDebug; /* MBAR_SDMA + 0x6c sdAdsTop */
88  volatile uint32 Value1; /* MBAR_SDMA + 0x70 sdDbg */
89  volatile uint32 Value2; /* MBAR_SDMA + 0x74 sdDbg */
90  volatile uint32 Control; /* MBAR_SDMA + 0x78 sdDbg */
91  volatile uint32 Status; /* MBAR_SDMA + 0x7c sdDbg */
92  volatile uint32 PTDDebug; /* MBAR_SDMA + 0x80 sdPtd */
93 } sdma_regs;
94 
95 #define SDMA_PTDCNTRL_TI 0x8000
96 #define SDMA_PTDCNTRL_TEA 0x4000
97 #define SDMA_PTDCNTRL_HE 0x2000
98 #define SDMA_PTDCNTRL_PE 0x0001
99 
100 #define SDMA_CREQSELECT_REQ31_MASK (~0xC0000000UL)
101 #define SDMA_CREQSELECT_REQ30_MASK (~0x30000000UL)
102 #define SDMA_CREQSELECT_REQ29_MASK (~0x0C000000UL)
103 #define SDMA_CREQSELECT_REQ28_MASK (~0x03000000UL)
104 #define SDMA_CREQSELECT_REQ27_MASK (~0x00C00000UL)
105 #define SDMA_CREQSELECT_REQ26_MASK (~0x00300000UL)
106 #define SDMA_CREQSELECT_REQ25_MASK (~0x000C0000UL)
107 #define SDMA_CREQSELECT_REQ24_MASK (~0x00030000UL)
108 #define SDMA_CREQSELECT_REQ23_MASK (~0x0000C000UL)
109 #define SDMA_CREQSELECT_REQ22_MASK (~0x00003000UL)
110 #define SDMA_CREQSELECT_REQ21_MASK (~0x00000C00UL)
111 #define SDMA_CREQSELECT_REQ20_MASK (~0x00000300UL)
112 #define SDMA_CREQSELECT_REQ19_MASK (~0x000000C0UL)
113 #define SDMA_CREQSELECT_REQ18_MASK (~0x00000030UL)
114 #define SDMA_CREQSELECT_REQ17_MASK (~0x0000000CUL)
115 #define SDMA_CREQSELECT_REQ16_MASK (~0x00000003UL)
116 
117 #define SDMA_CREQSELECT_REQ31_ALWAYS31 0xC0000000UL
118 #define SDMA_CREQSELECT_REQ30_ALWAYS30 0x30000000UL
119 #define SDMA_CREQSELECT_REQ29_ALWAYS29 0x0C000000UL
120 #define SDMA_CREQSELECT_REQ28_ALWAYS28 0x03000000UL
121 #define SDMA_CREQSELECT_REQ27_ALWAYS27 0x00C00000UL
122 #define SDMA_CREQSELECT_REQ26_ALWAYS26 0x00300000UL
123 #define SDMA_CREQSELECT_REQ25_ALWAYS25 0x000C0000UL
124 #define SDMA_CREQSELECT_REQ24_ALWAYS24 0x00030000UL
125 #define SDMA_CREQSELECT_REQ23_ALWAYS23 0x0000C000UL
126 #define SDMA_CREQSELECT_REQ22_ALWAYS22 0x00003000UL
127 #define SDMA_CREQSELECT_REQ21_ALWAYS21 0x00000C00UL
128 #define SDMA_CREQSELECT_REQ20_ALWAYS20 0x00000300UL
129 #define SDMA_CREQSELECT_REQ19_ALWAYS19 0x000000C0UL
130 #define SDMA_CREQSELECT_REQ18_ALWAYS18 0x00000030UL
131 #define SDMA_CREQSELECT_REQ17_ALWAYS17 0x0000000CUL
132 #define SDMA_CREQSELECT_REQ16_ALWAYS16 0x00000003UL
133 
134 #define SDMA_CREQSELECT_REQ31_SCTIMER7 0x00000000UL
135 #define SDMA_CREQSELECT_REQ30_SCTIMER6 0x00000000UL
136 #define SDMA_CREQSELECT_REQ29_SCTIMER5 0x00000000UL
137 #define SDMA_CREQSELECT_REQ28_SCTIMER4 0x00000000UL
138 #define SDMA_CREQSELECT_REQ27_SCTIMER3 0x00000000UL
139 #define SDMA_CREQSELECT_REQ26_PSC6_TX 0x00000000UL
140 #define SDMA_CREQSELECT_REQ25_PSC6_RX 0x00000000UL
141 #define SDMA_CREQSELECT_REQ24_I2C1_TX 0x00000000UL
142 #define SDMA_CREQSELECT_REQ23_I2C1_RX 0x00000000UL
143 #define SDMA_CREQSELECT_REQ22_I2C2_TX 0x00000000UL
144 #define SDMA_CREQSELECT_REQ21_I2C2_RX 0x00000000UL
145 #define SDMA_CREQSELECT_REQ20_PSC4_TX 0x00000000UL
146 #define SDMA_CREQSELECT_REQ19_PSC4_RX 0x00000000UL
147 #define SDMA_CREQSELECT_REQ18_PSC5_TX 0x00000000UL
148 #define SDMA_CREQSELECT_REQ17_PSC5_RX 0x00000000UL
149 #define SDMA_CREQSELECT_REQ16_LP 0x00000000UL
150 
151 #define SDMA_CREQSELECT_ALWAYS30 0xC0000000UL
152 
153 #endif /* __MGT5200_SDMA_H */
sdma_register_set
Definition: sdma.h:28
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