component_matrix.h

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#ifndef _SAMS70_MATRIX_COMPONENT_
#define _SAMS70_MATRIX_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  __IO uint32_t MATRIX_MCFG0;   
  __IO uint32_t MATRIX_MCFG1;   
  __IO uint32_t MATRIX_MCFG2;   
  __IO uint32_t MATRIX_MCFG3;   
  __IO uint32_t MATRIX_MCFG4;   
  __IO uint32_t MATRIX_MCFG5;   
  __IO uint32_t MATRIX_MCFG6;   
  __I  uint32_t Reserved1[1];
  __IO uint32_t MATRIX_MCFG8;   
  __I  uint32_t Reserved2[7];
  __IO uint32_t MATRIX_SCFG[9]; 
  __I  uint32_t Reserved3[7];
  __IO uint32_t MATRIX_PRAS0;   
  __IO uint32_t MATRIX_PRBS0;   
  __IO uint32_t MATRIX_PRAS1;   
  __IO uint32_t MATRIX_PRBS1;   
  __IO uint32_t MATRIX_PRAS2;   
  __IO uint32_t MATRIX_PRBS2;   
  __IO uint32_t MATRIX_PRAS3;   
  __IO uint32_t MATRIX_PRBS3;   
  __IO uint32_t MATRIX_PRAS4;   
  __IO uint32_t MATRIX_PRBS4;   
  __IO uint32_t MATRIX_PRAS5;   
  __IO uint32_t MATRIX_PRBS5;   
  __IO uint32_t MATRIX_PRAS6;   
  __IO uint32_t MATRIX_PRBS6;   
  __IO uint32_t MATRIX_PRAS7;   
  __IO uint32_t MATRIX_PRBS7;   
  __IO uint32_t MATRIX_PRAS8;   
  __IO uint32_t MATRIX_PRBS8;   
  __I  uint32_t Reserved4[14];
  __IO uint32_t MATRIX_MRCR;    
  __I  uint32_t Reserved5[4];
  __IO uint32_t CCFG_SYSIO;     
  __I  uint32_t Reserved6[3];
  __IO uint32_t CCFG_SMCNFCS;   
  __I  uint32_t Reserved7[47];
  __IO uint32_t MATRIX_WPMR;    
  __I  uint32_t MATRIX_WPSR;    
} Matrix;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
#define MATRIX_MCFG0_ULBT_Pos 0
#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) 
#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
#define   MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
#define MATRIX_MCFG1_ULBT_Pos 0
#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) 
#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
#define   MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
#define MATRIX_MCFG2_ULBT_Pos 0
#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) 
#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
#define   MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
#define MATRIX_MCFG3_ULBT_Pos 0
#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) 
#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
#define   MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
#define MATRIX_MCFG4_ULBT_Pos 0
#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) 
#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
#define   MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
#define MATRIX_MCFG5_ULBT_Pos 0
#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) 
#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
#define   MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
#define MATRIX_MCFG6_ULBT_Pos 0
#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) 
#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
#define   MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
#define MATRIX_MCFG8_ULBT_Pos 0
#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) 
#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
#define   MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) 
#define   MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) 
#define   MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) 
#define   MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) 
#define   MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) 
#define   MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) 
#define   MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) 
#define   MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) 
/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) 
#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) 
#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
#define   MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) 
#define   MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) 
#define   MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) 
#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) 
#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
#define MATRIX_PRAS0_M0PR_Pos 0
#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) 
#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
#define MATRIX_PRAS0_M1PR_Pos 4
#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) 
#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
#define MATRIX_PRAS0_M2PR_Pos 8
#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) 
#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
#define MATRIX_PRAS0_M3PR_Pos 12
#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) 
#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
#define MATRIX_PRAS0_M4PR_Pos 16
#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) 
#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
#define MATRIX_PRAS0_M5PR_Pos 20
#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) 
#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
#define MATRIX_PRAS0_M6PR_Pos 24
#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos) 
#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos)))
/* -------- MATRIX_PRBS0 : (MATRIX Offset: 0x0084) Priority Register B for Slave 0 -------- */
#define MATRIX_PRBS0_M8PR_Pos 0
#define MATRIX_PRBS0_M8PR_Msk (0x3u << MATRIX_PRBS0_M8PR_Pos) 
#define MATRIX_PRBS0_M8PR(value) ((MATRIX_PRBS0_M8PR_Msk & ((value) << MATRIX_PRBS0_M8PR_Pos)))
/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
#define MATRIX_PRAS1_M0PR_Pos 0
#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) 
#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
#define MATRIX_PRAS1_M1PR_Pos 4
#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) 
#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
#define MATRIX_PRAS1_M2PR_Pos 8
#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) 
#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
#define MATRIX_PRAS1_M3PR_Pos 12
#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) 
#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
#define MATRIX_PRAS1_M4PR_Pos 16
#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) 
#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
#define MATRIX_PRAS1_M5PR_Pos 20
#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) 
#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
#define MATRIX_PRAS1_M6PR_Pos 24
#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos) 
#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos)))
/* -------- MATRIX_PRBS1 : (MATRIX Offset: 0x008C) Priority Register B for Slave 1 -------- */
#define MATRIX_PRBS1_M8PR_Pos 0
#define MATRIX_PRBS1_M8PR_Msk (0x3u << MATRIX_PRBS1_M8PR_Pos) 
#define MATRIX_PRBS1_M8PR(value) ((MATRIX_PRBS1_M8PR_Msk & ((value) << MATRIX_PRBS1_M8PR_Pos)))
/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
#define MATRIX_PRAS2_M0PR_Pos 0
#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) 
#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
#define MATRIX_PRAS2_M1PR_Pos 4
#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) 
#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
#define MATRIX_PRAS2_M2PR_Pos 8
#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) 
#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
#define MATRIX_PRAS2_M3PR_Pos 12
#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) 
#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
#define MATRIX_PRAS2_M4PR_Pos 16
#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) 
#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
#define MATRIX_PRAS2_M5PR_Pos 20
#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) 
#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
#define MATRIX_PRAS2_M6PR_Pos 24
#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos) 
#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos)))
/* -------- MATRIX_PRBS2 : (MATRIX Offset: 0x0094) Priority Register B for Slave 2 -------- */
#define MATRIX_PRBS2_M8PR_Pos 0
#define MATRIX_PRBS2_M8PR_Msk (0x3u << MATRIX_PRBS2_M8PR_Pos) 
#define MATRIX_PRBS2_M8PR(value) ((MATRIX_PRBS2_M8PR_Msk & ((value) << MATRIX_PRBS2_M8PR_Pos)))
/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
#define MATRIX_PRAS3_M0PR_Pos 0
#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) 
#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
#define MATRIX_PRAS3_M1PR_Pos 4
#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) 
#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
#define MATRIX_PRAS3_M2PR_Pos 8
#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) 
#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
#define MATRIX_PRAS3_M3PR_Pos 12
#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) 
#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
#define MATRIX_PRAS3_M4PR_Pos 16
#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) 
#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
#define MATRIX_PRAS3_M5PR_Pos 20
#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) 
#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
#define MATRIX_PRAS3_M6PR_Pos 24
#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos) 
#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos)))
/* -------- MATRIX_PRBS3 : (MATRIX Offset: 0x009C) Priority Register B for Slave 3 -------- */
#define MATRIX_PRBS3_M8PR_Pos 0
#define MATRIX_PRBS3_M8PR_Msk (0x3u << MATRIX_PRBS3_M8PR_Pos) 
#define MATRIX_PRBS3_M8PR(value) ((MATRIX_PRBS3_M8PR_Msk & ((value) << MATRIX_PRBS3_M8PR_Pos)))
/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
#define MATRIX_PRAS4_M0PR_Pos 0
#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) 
#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
#define MATRIX_PRAS4_M1PR_Pos 4
#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) 
#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
#define MATRIX_PRAS4_M2PR_Pos 8
#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) 
#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
#define MATRIX_PRAS4_M3PR_Pos 12
#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) 
#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
#define MATRIX_PRAS4_M4PR_Pos 16
#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) 
#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
#define MATRIX_PRAS4_M5PR_Pos 20
#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) 
#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
#define MATRIX_PRAS4_M6PR_Pos 24
#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos) 
#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos)))
/* -------- MATRIX_PRBS4 : (MATRIX Offset: 0x00A4) Priority Register B for Slave 4 -------- */
#define MATRIX_PRBS4_M8PR_Pos 0
#define MATRIX_PRBS4_M8PR_Msk (0x3u << MATRIX_PRBS4_M8PR_Pos) 
#define MATRIX_PRBS4_M8PR(value) ((MATRIX_PRBS4_M8PR_Msk & ((value) << MATRIX_PRBS4_M8PR_Pos)))
/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
#define MATRIX_PRAS5_M0PR_Pos 0
#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) 
#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
#define MATRIX_PRAS5_M1PR_Pos 4
#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) 
#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
#define MATRIX_PRAS5_M2PR_Pos 8
#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) 
#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
#define MATRIX_PRAS5_M3PR_Pos 12
#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) 
#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
#define MATRIX_PRAS5_M4PR_Pos 16
#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) 
#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
#define MATRIX_PRAS5_M5PR_Pos 20
#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) 
#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
#define MATRIX_PRAS5_M6PR_Pos 24
#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos) 
#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos)))
/* -------- MATRIX_PRBS5 : (MATRIX Offset: 0x00AC) Priority Register B for Slave 5 -------- */
#define MATRIX_PRBS5_M8PR_Pos 0
#define MATRIX_PRBS5_M8PR_Msk (0x3u << MATRIX_PRBS5_M8PR_Pos) 
#define MATRIX_PRBS5_M8PR(value) ((MATRIX_PRBS5_M8PR_Msk & ((value) << MATRIX_PRBS5_M8PR_Pos)))
/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
#define MATRIX_PRAS6_M0PR_Pos 0
#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) 
#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
#define MATRIX_PRAS6_M1PR_Pos 4
#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) 
#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
#define MATRIX_PRAS6_M2PR_Pos 8
#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) 
#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
#define MATRIX_PRAS6_M3PR_Pos 12
#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) 
#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
#define MATRIX_PRAS6_M4PR_Pos 16
#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) 
#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
#define MATRIX_PRAS6_M5PR_Pos 20
#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) 
#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
#define MATRIX_PRAS6_M6PR_Pos 24
#define MATRIX_PRAS6_M6PR_Msk (0x3u << MATRIX_PRAS6_M6PR_Pos) 
#define MATRIX_PRAS6_M6PR(value) ((MATRIX_PRAS6_M6PR_Msk & ((value) << MATRIX_PRAS6_M6PR_Pos)))
/* -------- MATRIX_PRBS6 : (MATRIX Offset: 0x00B4) Priority Register B for Slave 6 -------- */
#define MATRIX_PRBS6_M8PR_Pos 0
#define MATRIX_PRBS6_M8PR_Msk (0x3u << MATRIX_PRBS6_M8PR_Pos) 
#define MATRIX_PRBS6_M8PR(value) ((MATRIX_PRBS6_M8PR_Msk & ((value) << MATRIX_PRBS6_M8PR_Pos)))
/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
#define MATRIX_PRAS7_M0PR_Pos 0
#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) 
#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
#define MATRIX_PRAS7_M1PR_Pos 4
#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) 
#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
#define MATRIX_PRAS7_M2PR_Pos 8
#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) 
#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
#define MATRIX_PRAS7_M3PR_Pos 12
#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) 
#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
#define MATRIX_PRAS7_M4PR_Pos 16
#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) 
#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
#define MATRIX_PRAS7_M5PR_Pos 20
#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) 
#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
#define MATRIX_PRAS7_M6PR_Pos 24
#define MATRIX_PRAS7_M6PR_Msk (0x3u << MATRIX_PRAS7_M6PR_Pos) 
#define MATRIX_PRAS7_M6PR(value) ((MATRIX_PRAS7_M6PR_Msk & ((value) << MATRIX_PRAS7_M6PR_Pos)))
/* -------- MATRIX_PRBS7 : (MATRIX Offset: 0x00BC) Priority Register B for Slave 7 -------- */
#define MATRIX_PRBS7_M8PR_Pos 0
#define MATRIX_PRBS7_M8PR_Msk (0x3u << MATRIX_PRBS7_M8PR_Pos) 
#define MATRIX_PRBS7_M8PR(value) ((MATRIX_PRBS7_M8PR_Msk & ((value) << MATRIX_PRBS7_M8PR_Pos)))
/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
#define MATRIX_PRAS8_M0PR_Pos 0
#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) 
#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
#define MATRIX_PRAS8_M1PR_Pos 4
#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) 
#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
#define MATRIX_PRAS8_M2PR_Pos 8
#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) 
#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
#define MATRIX_PRAS8_M3PR_Pos 12
#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) 
#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
#define MATRIX_PRAS8_M4PR_Pos 16
#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) 
#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
#define MATRIX_PRAS8_M5PR_Pos 20
#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) 
#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
#define MATRIX_PRAS8_M6PR_Pos 24
#define MATRIX_PRAS8_M6PR_Msk (0x3u << MATRIX_PRAS8_M6PR_Pos) 
#define MATRIX_PRAS8_M6PR(value) ((MATRIX_PRAS8_M6PR_Msk & ((value) << MATRIX_PRAS8_M6PR_Pos)))
/* -------- MATRIX_PRBS8 : (MATRIX Offset: 0x00C4) Priority Register B for Slave 8 -------- */
#define MATRIX_PRBS8_M8PR_Pos 0
#define MATRIX_PRBS8_M8PR_Msk (0x3u << MATRIX_PRBS8_M8PR_Pos) 
#define MATRIX_PRBS8_M8PR(value) ((MATRIX_PRBS8_M8PR_Msk & ((value) << MATRIX_PRBS8_M8PR_Pos)))
/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
#define MATRIX_MRCR_RCB0 (0x1u << 0) 
#define MATRIX_MRCR_RCB1 (0x1u << 1) 
#define MATRIX_MRCR_RCB2 (0x1u << 2) 
#define MATRIX_MRCR_RCB3 (0x1u << 3) 
#define MATRIX_MRCR_RCB4 (0x1u << 4) 
#define MATRIX_MRCR_RCB5 (0x1u << 5) 
#define MATRIX_MRCR_RCB6 (0x1u << 6) 
#define MATRIX_MRCR_RCB8 (0x1u << 8) 
/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */
#define CCFG_SYSIO_SYSIO4 (0x1u << 4) 
#define CCFG_SYSIO_SYSIO5 (0x1u << 5) 
#define CCFG_SYSIO_SYSIO6 (0x1u << 6) 
#define CCFG_SYSIO_SYSIO7 (0x1u << 7) 
#define CCFG_SYSIO_SYSIO12 (0x1u << 12) 
/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) 
#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) 
#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) 
#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) 
#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) 
/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
#define MATRIX_WPMR_WPEN (0x1u << 0) 
#define MATRIX_WPMR_WPKEY_Pos 8
#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) 
#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
#define   MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) 
/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
#define MATRIX_WPSR_WPVS (0x1u << 0) 
#define MATRIX_WPSR_WPVSRC_Pos 8
#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) 


#endif /* _SAMS70_MATRIX_COMPONENT_ */