30 #ifndef _SAME70_WDT_COMPONENT_ 31 #define _SAME70_WDT_COMPONENT_ 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 #define WDT_CR_WDRSTT (0x1u << 0) 49 #define WDT_CR_KEY_Pos 24 50 #define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) 51 #define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) 52 #define WDT_CR_KEY_PASSWD (0xA5u << 24) 54 #define WDT_MR_WDV_Pos 0 55 #define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) 56 #define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) 57 #define WDT_MR_WDFIEN (0x1u << 12) 58 #define WDT_MR_WDRSTEN (0x1u << 13) 59 #define WDT_MR_WDDIS (0x1u << 15) 60 #define WDT_MR_WDD_Pos 16 61 #define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) 62 #define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) 63 #define WDT_MR_WDDBGHLT (0x1u << 28) 64 #define WDT_MR_WDIDLEHLT (0x1u << 29) 66 #define WDT_SR_WDUNF (0x1u << 0) 67 #define WDT_SR_WDERR (0x1u << 1) __I uint32_t WDT_SR
(Wdt Offset: 0x08) Status Register
Definition: component_wdt.h:44
#define __IO
Definition: core_cm7.h:287
#define __O
Definition: core_cm7.h:286
__IO uint32_t WDT_MR
(Wdt Offset: 0x04) Mode Register
Definition: component_wdt.h:43
__O uint32_t WDT_CR
(Wdt Offset: 0x00) Control Register
Definition: component_wdt.h:42
Wdt hardware registers.
Definition: component_wdt.h:41
#define __I
Definition: core_cm7.h:284