RTEMS  5.0.0
s25fl1.h
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28 /* ---------------------------------------------------------------------------- */
29 
37 #ifndef S25FL1_H
38 #define S25FL1_H
39 #define USE_QSPI_DMA
40 /*----------------------------------------------------------------------------
41  * Macros
42  *----------------------------------------------------------------------------*/
43 
44 #define Size(pAt25) ((pAt25)->pDesc->size)
45 #define PageSize(pAt25) ((pAt25)->pDesc->pageSize)
46 #define BlockSize(pAt25) ((pAt25)->pDesc->blockSize)
47 #define Name(pAt25) ((pAt25)->pDesc->name)
48 #define ManId(pAt25) (((pAt25)->pDesc->jedecId) & 0xFF)
49 #define PageNumber(pAt25) (Size(pAt25) / PageSize(pAt25))
50 #define BlockNumber(pAt25) (Size(pAt25) / BlockSize(pAt25))
51 #define PagePerBlock(pAt25) (BlockSize(pAt25) / PageSize(pAt25))
52 #define BlockEraseCmd(pAt25) ((pAt25)->pDesc->blockEraseCmd)
53 
54 /*----------------------------------------------------------------------------
55  * Local definitions
56  *----------------------------------------------------------------------------*/
57 
59 #define ERROR_PROTECTED 1
60 
61 #define ERROR_BUSY 2
62 
63 #define ERROR_PROGRAM 3
64 
65 #define ERROR_SPI 4
66 
68 #define STATUS_RDYBSY (1 << 0)
69 
70 #define STATUS_RDYBSY_READY (0 << 0)
71 
72 #define STATUS_RDYBSY_BUSY (1 << 0)
73 
74 #define STATUS_WEL (1 << 1)
75 
76 #define STATUS_WEL_DISABLED (0 << 1)
77 
78 #define STATUS_WEL_ENABLED (1 << 1)
79 
80 #define STATUS_SWP (3 << 2)
81 
82 #define STATUS_SWP_PROTALL (3 << 2)
83 
84 #define STATUS_SWP_PROTSOME (1 << 2)
85 
86 #define STATUS_SWP_PROTNONE (0 << 2)
87 
88 #define STATUS_WPP (1 << 4)
89 
90 #define STATUS_WPP_NOTASSERTED (0 << 4)
91 
92 #define STATUS_WPP_ASSERTED (1 << 4)
93 
94 #define STATUS_EPE (1 << 5)
95 
96 #define STATUS_EPE_SUCCESS (0 << 5)
97 
98 #define STATUS_EPE_ERROR (1 << 5)
99 
100 #define STATUS_SPRL (1 << 7)
101 
102 #define STATUS_SPRL_UNLOCKED (0 << 7)
103 
104 #define STATUS_SPRL_LOCKED (1 << 7)
105 
107 #define STATUS_QUAD_ENABLE (1 << 1)
108 
109 #define STATUS_WRAP_ENABLE (0 << 4)
110 
112 #define STATUS_LATENCY_CTRL (0xF << 0)
113 
114 #define STATUS_WRAP_BYTE (1 << 5)
115 
116 #define BLOCK_PROTECT_Msk (7 << 2)
117 
118 #define TOP_BTM_PROTECT_Msk (1 << 5)
119 
120 #define SEC_PROTECT_Msk (1 << 6)
121 
122 #define CHIP_PROTECT_Msk (0x1F << 2)
123 
125 #define READ_ARRAY 0x0B
126 
127 #define READ_ARRAY_LF 0x03
128 
129 #define READ_ARRAY_DUAL 0x3B
130 
131 #define READ_ARRAY_QUAD 0x6B
132 
133 #define READ_ARRAY_DUAL_IO 0xBB
134 
135 #define READ_ARRAY_QUAD_IO 0xEB
136 
137 #define BLOCK_ERASE_4K 0x20
138 
139 #define BLOCK_ERASE_32K 0x52
140 
141 #define BLOCK_ERASE_64K 0xD8
142 
143 #define CHIP_ERASE_1 0x60
144 
145 #define CHIP_ERASE_2 0xC7
146 
147 #define BYTE_PAGE_PROGRAM 0x02
148 
149 #define SEQUENTIAL_PROGRAM_1 0xAD
150 
151 #define SEQUENTIAL_PROGRAM_2 0xAF
152 
153 #define WRITE_ENABLE 0x06
154 
155 #define WRITE_DISABLE 0x04
156 
157 #define PROTECT_SECTOR 0x36
158 
159 #define UNPROTECT_SECTOR 0x39
160 
161 #define READ_SECTOR_PROT 0x3C
162 
163 #define READ_STATUS_1 0x05
164 
165 #define READ_STATUS_2 0x35
166 
167 #define READ_STATUS_3 0x33
168 
169 #define WRITE_STATUS 0x01
170 
171 #define READ_JEDEC_ID 0x9F
172 
173 #define DEEP_PDOWN 0xB9
174 
175 #define RES_DEEP_PDOWN 0xAB
176 
177 #define SOFT_RESET_ENABLE 0x66
178 
179 #define SOFT_RESET 0x99
180 
181 #define WRAP_ENABLE 0x77
182 
183 #define CONT_MODE_RESET 0xFF
184 
186 #define ATMEL_SPI_FLASH 0x1F
187 #define ST_SPI_FLASH 0x20
188 #define WINBOND_SPI_FLASH 0xEF
189 #define MACRONIX_SPI_FLASH 0xC2
190 #define SST_SPI_FLASH 0xBF
191 
192 /*----------------------------------------------------------------------------
193  * Exported functions
194  *----------------------------------------------------------------------------*/
195 
196 uint32_t S25FL1D_ReadJedecId(void);
197 
198 void S25FL1D_InitFlashInterface(uint8_t Mode);
199 
200 void S25FL1D_SoftReset(void);
201 
202 void S25FL1D_ContReadModeReset(void);
203 unsigned char S25FL1D_Unprotect(void);
204 
205 unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size);
206 
207 void S25FL1D_QuadMode(uint8_t Enable);
208 
209 void S25FL1D_EnableWrap(uint8_t ByetAlign);
210 
211 void S25FL1D_SetReadLatencyControl(uint8_t Latency);
212 
213 unsigned char S25FL1D_EraseChip(void);
214 
215 unsigned char S25FL1D_EraseSector(unsigned int address);
216 
217 unsigned char S25FL1D_Erase64KBlock(unsigned int address);
218 
219 unsigned char S25FL1D_Write(
220  uint32_t *pData,
221  uint32_t size,
222  uint32_t address,
223  uint8_t Secure);
224 
225 extern unsigned char S25FL1D_Read(
226  uint32_t *pData,
227  uint32_t size,
228  uint32_t address);
229 
230 extern unsigned char S25FL1D_ReadDual(
231  uint32_t *pData,
232  uint32_t size,
233  uint32_t address);
234 
235 extern unsigned char S25FL1D_ReadQuad(
236  uint32_t *pData,
237  uint32_t size,
238  uint32_t address);
239 
240 extern unsigned char S25FL1D_ReadDualIO(
241  uint32_t *pData,
242  uint32_t size,
243  uint32_t address,
244  uint8_t ContMode,
245  uint8_t Secure);
246 
247 extern unsigned char S25FL1D_ReadQuadIO(
248  uint32_t *pData,
249  uint32_t size,
250  uint32_t address,
251  uint8_t ContMode,
252  uint8_t Secure);
253 
254 #endif // #ifndef S25FL1_H
255 
unsigned size
Definition: tte.h:74