RTEMS
5.0.0
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RISCV utility. More...
Go to the source code of this file.
Macros | |
#define | MSTATUS_UIE 0x00000001 |
#define | MSTATUS_SIE 0x00000002 |
#define | MSTATUS_HIE 0x00000004 |
#define | MSTATUS_MIE 0x00000008 |
#define | MSTATUS_UPIE 0x00000010 |
#define | MSTATUS_SPIE 0x00000020 |
#define | MSTATUS_HPIE 0x00000040 |
#define | MSTATUS_MPIE 0x00000080 |
#define | MSTATUS_SPP 0x00000100 |
#define | MSTATUS_HPP 0x00000600 |
#define | MSTATUS_MPP 0x00001800 |
#define | MSTATUS_FS 0x00006000 |
#define | MSTATUS_XS 0x00018000 |
#define | MSTATUS_MPRV 0x00020000 |
#define | MSTATUS_SUM 0x00040000 |
#define | MSTATUS_MXR 0x00080000 |
#define | MSTATUS_TVM 0x00100000 |
#define | MSTATUS_TW 0x00200000 |
#define | MSTATUS_TSR 0x00400000 |
#define | MSTATUS32_SD 0x80000000 |
#define | MSTATUS64_SD 0x8000000000000000 |
#define | SSTATUS_UIE 0x00000001 |
#define | SSTATUS_SIE 0x00000002 |
#define | SSTATUS_UPIE 0x00000010 |
#define | SSTATUS_SPIE 0x00000020 |
#define | SSTATUS_SPP 0x00000100 |
#define | SSTATUS_FS 0x00006000 |
#define | SSTATUS_XS 0x00018000 |
#define | SSTATUS_SUM 0x00040000 |
#define | SSTATUS_MXR 0x00080000 |
#define | SSTATUS32_SD 0x80000000 |
#define | SSTATUS64_SD 0x8000000000000000 |
#define | DCSR_XDEBUGVER (3U<<30) |
#define | DCSR_NDRESET (1<<29) |
#define | DCSR_FULLRESET (1<<28) |
#define | DCSR_EBREAKM (1<<15) |
#define | DCSR_EBREAKH (1<<14) |
#define | DCSR_EBREAKS (1<<13) |
#define | DCSR_EBREAKU (1<<12) |
#define | DCSR_STOPCYCLE (1<<10) |
#define | DCSR_STOPTIME (1<<9) |
#define | DCSR_CAUSE (7<<6) |
#define | DCSR_DEBUGINT (1<<5) |
#define | DCSR_HALT (1<<3) |
#define | DCSR_STEP (1<<2) |
#define | DCSR_PRV (3<<0) |
#define | DCSR_CAUSE_NONE 0 |
#define | DCSR_CAUSE_SWBP 1 |
#define | DCSR_CAUSE_HWBP 2 |
#define | DCSR_CAUSE_DEBUGINT 3 |
#define | DCSR_CAUSE_STEP 4 |
#define | DCSR_CAUSE_HALT 5 |
#define | MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) |
#define | MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) |
#define | MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) |
#define | MCONTROL_SELECT (1<<19) |
#define | MCONTROL_TIMING (1<<18) |
#define | MCONTROL_ACTION (0x3f<<12) |
#define | MCONTROL_CHAIN (1<<11) |
#define | MCONTROL_MATCH (0xf<<7) |
#define | MCONTROL_M (1<<6) |
#define | MCONTROL_H (1<<5) |
#define | MCONTROL_S (1<<4) |
#define | MCONTROL_U (1<<3) |
#define | MCONTROL_EXECUTE (1<<2) |
#define | MCONTROL_STORE (1<<1) |
#define | MCONTROL_LOAD (1<<0) |
#define | MCONTROL_TYPE_NONE 0 |
#define | MCONTROL_TYPE_MATCH 2 |
#define | MCONTROL_ACTION_DEBUG_EXCEPTION 0 |
#define | MCONTROL_ACTION_DEBUG_MODE 1 |
#define | MCONTROL_ACTION_TRACE_START 2 |
#define | MCONTROL_ACTION_TRACE_STOP 3 |
#define | MCONTROL_ACTION_TRACE_EMIT 4 |
#define | MCONTROL_MATCH_EQUAL 0 |
#define | MCONTROL_MATCH_NAPOT 1 |
#define | MCONTROL_MATCH_GE 2 |
#define | MCONTROL_MATCH_LT 3 |
#define | MCONTROL_MATCH_MASK_LOW 4 |
#define | MCONTROL_MATCH_MASK_HIGH 5 |
#define | MIP_SSIP (1 << IRQ_S_SOFT) |
#define | MIP_HSIP (1 << IRQ_H_SOFT) |
#define | MIP_MSIP (1 << IRQ_M_SOFT) |
#define | MIP_STIP (1 << IRQ_S_TIMER) |
#define | MIP_HTIP (1 << IRQ_H_TIMER) |
#define | MIP_MTIP (1 << IRQ_M_TIMER) |
#define | MIP_SEIP (1 << IRQ_S_EXT) |
#define | MIP_HEIP (1 << IRQ_H_EXT) |
#define | MIP_MEIP (1 << IRQ_M_EXT) |
#define | SIP_SSIP MIP_SSIP |
#define | SIP_STIP MIP_STIP |
#define | PRV_U 0 |
#define | PRV_S 1 |
#define | PRV_H 2 |
#define | PRV_M 3 |
#define | SPTBR32_MODE 0x80000000 |
#define | SPTBR32_ASID 0x7FC00000 |
#define | SPTBR32_PPN 0x003FFFFF |
#define | SPTBR64_MODE 0xF000000000000000 |
#define | SPTBR64_ASID 0x0FFFF00000000000 |
#define | SPTBR64_PPN 0x00000FFFFFFFFFFF |
#define | SPTBR_MODE_OFF 0 |
#define | SPTBR_MODE_SV32 1 |
#define | SPTBR_MODE_SV39 8 |
#define | SPTBR_MODE_SV48 9 |
#define | SPTBR_MODE_SV57 10 |
#define | SPTBR_MODE_SV64 11 |
#define | PMP_R 0x01 |
#define | PMP_W 0x02 |
#define | PMP_X 0x04 |
#define | PMP_A 0x18 |
#define | PMP_L 0x80 |
#define | PMP_SHIFT 2 |
#define | PMP_TOR 0x08 |
#define | PMP_NA4 0x10 |
#define | PMP_NAPOT 0x18 |
#define | IRQ_S_SOFT 1 |
#define | IRQ_H_SOFT 2 |
#define | IRQ_M_SOFT 3 |
#define | IRQ_S_TIMER 5 |
#define | IRQ_H_TIMER 6 |
#define | IRQ_M_TIMER 7 |
#define | IRQ_S_EXT 9 |
#define | IRQ_H_EXT 10 |
#define | IRQ_M_EXT 11 |
#define | IRQ_COP 12 |
#define | IRQ_HOST 13 |
#define | DEFAULT_RSTVEC 0x00001000 |
#define | CLINT_BASE 0x02000000 |
#define | CLINT_SIZE 0x000c0000 |
#define | EXT_IO_BASE 0x40000000 |
#define | DRAM_BASE 0x80000000 |
#define | PTE_V 0x001 |
#define | PTE_R 0x002 |
#define | PTE_W 0x004 |
#define | PTE_X 0x008 |
#define | PTE_U 0x010 |
#define | PTE_G 0x020 |
#define | PTE_A 0x040 |
#define | PTE_D 0x080 |
#define | PTE_SOFT 0x300 |
#define | PTE_PPN_SHIFT 10 |
#define | PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) |
#define | RISCV_ENCODING_H |
#define | MATCH_BEQ 0x63 |
#define | MASK_BEQ 0x707f |
#define | MATCH_BNE 0x1063 |
#define | MASK_BNE 0x707f |
#define | MATCH_BLT 0x4063 |
#define | MASK_BLT 0x707f |
#define | MATCH_BGE 0x5063 |
#define | MASK_BGE 0x707f |
#define | MATCH_BLTU 0x6063 |
#define | MASK_BLTU 0x707f |
#define | MATCH_BGEU 0x7063 |
#define | MASK_BGEU 0x707f |
#define | MATCH_JALR 0x67 |
#define | MASK_JALR 0x707f |
#define | MATCH_JAL 0x6f |
#define | MASK_JAL 0x7f |
#define | MATCH_LUI 0x37 |
#define | MASK_LUI 0x7f |
#define | MATCH_AUIPC 0x17 |
#define | MASK_AUIPC 0x7f |
#define | MATCH_ADDI 0x13 |
#define | MASK_ADDI 0x707f |
#define | MATCH_SLLI 0x1013 |
#define | MASK_SLLI 0xfc00707f |
#define | MATCH_SLTI 0x2013 |
#define | MASK_SLTI 0x707f |
#define | MATCH_SLTIU 0x3013 |
#define | MASK_SLTIU 0x707f |
#define | MATCH_XORI 0x4013 |
#define | MASK_XORI 0x707f |
#define | MATCH_SRLI 0x5013 |
#define | MASK_SRLI 0xfc00707f |
#define | MATCH_SRAI 0x40005013 |
#define | MASK_SRAI 0xfc00707f |
#define | MATCH_ORI 0x6013 |
#define | MASK_ORI 0x707f |
#define | MATCH_ANDI 0x7013 |
#define | MASK_ANDI 0x707f |
#define | MATCH_ADD 0x33 |
#define | MASK_ADD 0xfe00707f |
#define | MATCH_SUB 0x40000033 |
#define | MASK_SUB 0xfe00707f |
#define | MATCH_SLL 0x1033 |
#define | MASK_SLL 0xfe00707f |
#define | MATCH_SLT 0x2033 |
#define | MASK_SLT 0xfe00707f |
#define | MATCH_SLTU 0x3033 |
#define | MASK_SLTU 0xfe00707f |
#define | MATCH_XOR 0x4033 |
#define | MASK_XOR 0xfe00707f |
#define | MATCH_SRL 0x5033 |
#define | MASK_SRL 0xfe00707f |
#define | MATCH_SRA 0x40005033 |
#define | MASK_SRA 0xfe00707f |
#define | MATCH_OR 0x6033 |
#define | MASK_OR 0xfe00707f |
#define | MATCH_AND 0x7033 |
#define | MASK_AND 0xfe00707f |
#define | MATCH_ADDIW 0x1b |
#define | MASK_ADDIW 0x707f |
#define | MATCH_SLLIW 0x101b |
#define | MASK_SLLIW 0xfe00707f |
#define | MATCH_SRLIW 0x501b |
#define | MASK_SRLIW 0xfe00707f |
#define | MATCH_SRAIW 0x4000501b |
#define | MASK_SRAIW 0xfe00707f |
#define | MATCH_ADDW 0x3b |
#define | MASK_ADDW 0xfe00707f |
#define | MATCH_SUBW 0x4000003b |
#define | MASK_SUBW 0xfe00707f |
#define | MATCH_SLLW 0x103b |
#define | MASK_SLLW 0xfe00707f |
#define | MATCH_SRLW 0x503b |
#define | MASK_SRLW 0xfe00707f |
#define | MATCH_SRAW 0x4000503b |
#define | MASK_SRAW 0xfe00707f |
#define | MATCH_LB 0x3 |
#define | MASK_LB 0x707f |
#define | MATCH_LH 0x1003 |
#define | MASK_LH 0x707f |
#define | MATCH_LW 0x2003 |
#define | MASK_LW 0x707f |
#define | MATCH_LD 0x3003 |
#define | MASK_LD 0x707f |
#define | MATCH_LBU 0x4003 |
#define | MASK_LBU 0x707f |
#define | MATCH_LHU 0x5003 |
#define | MASK_LHU 0x707f |
#define | MATCH_LWU 0x6003 |
#define | MASK_LWU 0x707f |
#define | MATCH_SB 0x23 |
#define | MASK_SB 0x707f |
#define | MATCH_SH 0x1023 |
#define | MASK_SH 0x707f |
#define | MATCH_SW 0x2023 |
#define | MASK_SW 0x707f |
#define | MATCH_SD 0x3023 |
#define | MASK_SD 0x707f |
#define | MATCH_FENCE 0xf |
#define | MASK_FENCE 0x707f |
#define | MATCH_FENCE_I 0x100f |
#define | MASK_FENCE_I 0x707f |
#define | MATCH_MUL 0x2000033 |
#define | MASK_MUL 0xfe00707f |
#define | MATCH_MULH 0x2001033 |
#define | MASK_MULH 0xfe00707f |
#define | MATCH_MULHSU 0x2002033 |
#define | MASK_MULHSU 0xfe00707f |
#define | MATCH_MULHU 0x2003033 |
#define | MASK_MULHU 0xfe00707f |
#define | MATCH_DIV 0x2004033 |
#define | MASK_DIV 0xfe00707f |
#define | MATCH_DIVU 0x2005033 |
#define | MASK_DIVU 0xfe00707f |
#define | MATCH_REM 0x2006033 |
#define | MASK_REM 0xfe00707f |
#define | MATCH_REMU 0x2007033 |
#define | MASK_REMU 0xfe00707f |
#define | MATCH_MULW 0x200003b |
#define | MASK_MULW 0xfe00707f |
#define | MATCH_DIVW 0x200403b |
#define | MASK_DIVW 0xfe00707f |
#define | MATCH_DIVUW 0x200503b |
#define | MASK_DIVUW 0xfe00707f |
#define | MATCH_REMW 0x200603b |
#define | MASK_REMW 0xfe00707f |
#define | MATCH_REMUW 0x200703b |
#define | MASK_REMUW 0xfe00707f |
#define | MATCH_AMOADD_W 0x202f |
#define | MASK_AMOADD_W 0xf800707f |
#define | MATCH_AMOXOR_W 0x2000202f |
#define | MASK_AMOXOR_W 0xf800707f |
#define | MATCH_AMOOR_W 0x4000202f |
#define | MASK_AMOOR_W 0xf800707f |
#define | MATCH_AMOAND_W 0x6000202f |
#define | MASK_AMOAND_W 0xf800707f |
#define | MATCH_AMOMIN_W 0x8000202f |
#define | MASK_AMOMIN_W 0xf800707f |
#define | MATCH_AMOMAX_W 0xa000202f |
#define | MASK_AMOMAX_W 0xf800707f |
#define | MATCH_AMOMINU_W 0xc000202f |
#define | MASK_AMOMINU_W 0xf800707f |
#define | MATCH_AMOMAXU_W 0xe000202f |
#define | MASK_AMOMAXU_W 0xf800707f |
#define | MATCH_AMOSWAP_W 0x800202f |
#define | MASK_AMOSWAP_W 0xf800707f |
#define | MATCH_LR_W 0x1000202f |
#define | MASK_LR_W 0xf9f0707f |
#define | MATCH_SC_W 0x1800202f |
#define | MASK_SC_W 0xf800707f |
#define | MATCH_AMOADD_D 0x302f |
#define | MASK_AMOADD_D 0xf800707f |
#define | MATCH_AMOXOR_D 0x2000302f |
#define | MASK_AMOXOR_D 0xf800707f |
#define | MATCH_AMOOR_D 0x4000302f |
#define | MASK_AMOOR_D 0xf800707f |
#define | MATCH_AMOAND_D 0x6000302f |
#define | MASK_AMOAND_D 0xf800707f |
#define | MATCH_AMOMIN_D 0x8000302f |
#define | MASK_AMOMIN_D 0xf800707f |
#define | MATCH_AMOMAX_D 0xa000302f |
#define | MASK_AMOMAX_D 0xf800707f |
#define | MATCH_AMOMINU_D 0xc000302f |
#define | MASK_AMOMINU_D 0xf800707f |
#define | MATCH_AMOMAXU_D 0xe000302f |
#define | MASK_AMOMAXU_D 0xf800707f |
#define | MATCH_AMOSWAP_D 0x800302f |
#define | MASK_AMOSWAP_D 0xf800707f |
#define | MATCH_LR_D 0x1000302f |
#define | MASK_LR_D 0xf9f0707f |
#define | MATCH_SC_D 0x1800302f |
#define | MASK_SC_D 0xf800707f |
#define | MATCH_ECALL 0x73 |
#define | MASK_ECALL 0xffffffff |
#define | MATCH_EBREAK 0x100073 |
#define | MASK_EBREAK 0xffffffff |
#define | MATCH_URET 0x200073 |
#define | MASK_URET 0xffffffff |
#define | MATCH_SRET 0x10200073 |
#define | MASK_SRET 0xffffffff |
#define | MATCH_MRET 0x30200073 |
#define | MASK_MRET 0xffffffff |
#define | MATCH_DRET 0x7b200073 |
#define | MASK_DRET 0xffffffff |
#define | MATCH_SFENCE_VMA 0x12000073 |
#define | MASK_SFENCE_VMA 0xfe007fff |
#define | MATCH_WFI 0x10500073 |
#define | MASK_WFI 0xffffffff |
#define | MATCH_CSRRW 0x1073 |
#define | MASK_CSRRW 0x707f |
#define | MATCH_CSRRS 0x2073 |
#define | MASK_CSRRS 0x707f |
#define | MATCH_CSRRC 0x3073 |
#define | MASK_CSRRC 0x707f |
#define | MATCH_CSRRWI 0x5073 |
#define | MASK_CSRRWI 0x707f |
#define | MATCH_CSRRSI 0x6073 |
#define | MASK_CSRRSI 0x707f |
#define | MATCH_CSRRCI 0x7073 |
#define | MASK_CSRRCI 0x707f |
#define | MATCH_FADD_S 0x53 |
#define | MASK_FADD_S 0xfe00007f |
#define | MATCH_FSUB_S 0x8000053 |
#define | MASK_FSUB_S 0xfe00007f |
#define | MATCH_FMUL_S 0x10000053 |
#define | MASK_FMUL_S 0xfe00007f |
#define | MATCH_FDIV_S 0x18000053 |
#define | MASK_FDIV_S 0xfe00007f |
#define | MATCH_FSGNJ_S 0x20000053 |
#define | MASK_FSGNJ_S 0xfe00707f |
#define | MATCH_FSGNJN_S 0x20001053 |
#define | MASK_FSGNJN_S 0xfe00707f |
#define | MATCH_FSGNJX_S 0x20002053 |
#define | MASK_FSGNJX_S 0xfe00707f |
#define | MATCH_FMIN_S 0x28000053 |
#define | MASK_FMIN_S 0xfe00707f |
#define | MATCH_FMAX_S 0x28001053 |
#define | MASK_FMAX_S 0xfe00707f |
#define | MATCH_FSQRT_S 0x58000053 |
#define | MASK_FSQRT_S 0xfff0007f |
#define | MATCH_FADD_D 0x2000053 |
#define | MASK_FADD_D 0xfe00007f |
#define | MATCH_FSUB_D 0xa000053 |
#define | MASK_FSUB_D 0xfe00007f |
#define | MATCH_FMUL_D 0x12000053 |
#define | MASK_FMUL_D 0xfe00007f |
#define | MATCH_FDIV_D 0x1a000053 |
#define | MASK_FDIV_D 0xfe00007f |
#define | MATCH_FSGNJ_D 0x22000053 |
#define | MASK_FSGNJ_D 0xfe00707f |
#define | MATCH_FSGNJN_D 0x22001053 |
#define | MASK_FSGNJN_D 0xfe00707f |
#define | MATCH_FSGNJX_D 0x22002053 |
#define | MASK_FSGNJX_D 0xfe00707f |
#define | MATCH_FMIN_D 0x2a000053 |
#define | MASK_FMIN_D 0xfe00707f |
#define | MATCH_FMAX_D 0x2a001053 |
#define | MASK_FMAX_D 0xfe00707f |
#define | MATCH_FCVT_S_D 0x40100053 |
#define | MASK_FCVT_S_D 0xfff0007f |
#define | MATCH_FCVT_D_S 0x42000053 |
#define | MASK_FCVT_D_S 0xfff0007f |
#define | MATCH_FSQRT_D 0x5a000053 |
#define | MASK_FSQRT_D 0xfff0007f |
#define | MATCH_FADD_Q 0x6000053 |
#define | MASK_FADD_Q 0xfe00007f |
#define | MATCH_FSUB_Q 0xe000053 |
#define | MASK_FSUB_Q 0xfe00007f |
#define | MATCH_FMUL_Q 0x16000053 |
#define | MASK_FMUL_Q 0xfe00007f |
#define | MATCH_FDIV_Q 0x1e000053 |
#define | MASK_FDIV_Q 0xfe00007f |
#define | MATCH_FSGNJ_Q 0x26000053 |
#define | MASK_FSGNJ_Q 0xfe00707f |
#define | MATCH_FSGNJN_Q 0x26001053 |
#define | MASK_FSGNJN_Q 0xfe00707f |
#define | MATCH_FSGNJX_Q 0x26002053 |
#define | MASK_FSGNJX_Q 0xfe00707f |
#define | MATCH_FMIN_Q 0x2e000053 |
#define | MASK_FMIN_Q 0xfe00707f |
#define | MATCH_FMAX_Q 0x2e001053 |
#define | MASK_FMAX_Q 0xfe00707f |
#define | MATCH_FCVT_S_Q 0x40300053 |
#define | MASK_FCVT_S_Q 0xfff0007f |
#define | MATCH_FCVT_Q_S 0x46000053 |
#define | MASK_FCVT_Q_S 0xfff0007f |
#define | MATCH_FCVT_D_Q 0x42300053 |
#define | MASK_FCVT_D_Q 0xfff0007f |
#define | MATCH_FCVT_Q_D 0x46100053 |
#define | MASK_FCVT_Q_D 0xfff0007f |
#define | MATCH_FSQRT_Q 0x5e000053 |
#define | MASK_FSQRT_Q 0xfff0007f |
#define | MATCH_FLE_S 0xa0000053 |
#define | MASK_FLE_S 0xfe00707f |
#define | MATCH_FLT_S 0xa0001053 |
#define | MASK_FLT_S 0xfe00707f |
#define | MATCH_FEQ_S 0xa0002053 |
#define | MASK_FEQ_S 0xfe00707f |
#define | MATCH_FLE_D 0xa2000053 |
#define | MASK_FLE_D 0xfe00707f |
#define | MATCH_FLT_D 0xa2001053 |
#define | MASK_FLT_D 0xfe00707f |
#define | MATCH_FEQ_D 0xa2002053 |
#define | MASK_FEQ_D 0xfe00707f |
#define | MATCH_FLE_Q 0xa6000053 |
#define | MASK_FLE_Q 0xfe00707f |
#define | MATCH_FLT_Q 0xa6001053 |
#define | MASK_FLT_Q 0xfe00707f |
#define | MATCH_FEQ_Q 0xa6002053 |
#define | MASK_FEQ_Q 0xfe00707f |
#define | MATCH_FCVT_W_S 0xc0000053 |
#define | MASK_FCVT_W_S 0xfff0007f |
#define | MATCH_FCVT_WU_S 0xc0100053 |
#define | MASK_FCVT_WU_S 0xfff0007f |
#define | MATCH_FCVT_L_S 0xc0200053 |
#define | MASK_FCVT_L_S 0xfff0007f |
#define | MATCH_FCVT_LU_S 0xc0300053 |
#define | MASK_FCVT_LU_S 0xfff0007f |
#define | MATCH_FMV_X_W 0xe0000053 |
#define | MASK_FMV_X_W 0xfff0707f |
#define | MATCH_FCLASS_S 0xe0001053 |
#define | MASK_FCLASS_S 0xfff0707f |
#define | MATCH_FCVT_W_D 0xc2000053 |
#define | MASK_FCVT_W_D 0xfff0007f |
#define | MATCH_FCVT_WU_D 0xc2100053 |
#define | MASK_FCVT_WU_D 0xfff0007f |
#define | MATCH_FCVT_L_D 0xc2200053 |
#define | MASK_FCVT_L_D 0xfff0007f |
#define | MATCH_FCVT_LU_D 0xc2300053 |
#define | MASK_FCVT_LU_D 0xfff0007f |
#define | MATCH_FMV_X_D 0xe2000053 |
#define | MASK_FMV_X_D 0xfff0707f |
#define | MATCH_FCLASS_D 0xe2001053 |
#define | MASK_FCLASS_D 0xfff0707f |
#define | MATCH_FCVT_W_Q 0xc6000053 |
#define | MASK_FCVT_W_Q 0xfff0007f |
#define | MATCH_FCVT_WU_Q 0xc6100053 |
#define | MASK_FCVT_WU_Q 0xfff0007f |
#define | MATCH_FCVT_L_Q 0xc6200053 |
#define | MASK_FCVT_L_Q 0xfff0007f |
#define | MATCH_FCVT_LU_Q 0xc6300053 |
#define | MASK_FCVT_LU_Q 0xfff0007f |
#define | MATCH_FMV_X_Q 0xe6000053 |
#define | MASK_FMV_X_Q 0xfff0707f |
#define | MATCH_FCLASS_Q 0xe6001053 |
#define | MASK_FCLASS_Q 0xfff0707f |
#define | MATCH_FCVT_S_W 0xd0000053 |
#define | MASK_FCVT_S_W 0xfff0007f |
#define | MATCH_FCVT_S_WU 0xd0100053 |
#define | MASK_FCVT_S_WU 0xfff0007f |
#define | MATCH_FCVT_S_L 0xd0200053 |
#define | MASK_FCVT_S_L 0xfff0007f |
#define | MATCH_FCVT_S_LU 0xd0300053 |
#define | MASK_FCVT_S_LU 0xfff0007f |
#define | MATCH_FMV_W_X 0xf0000053 |
#define | MASK_FMV_W_X 0xfff0707f |
#define | MATCH_FCVT_D_W 0xd2000053 |
#define | MASK_FCVT_D_W 0xfff0007f |
#define | MATCH_FCVT_D_WU 0xd2100053 |
#define | MASK_FCVT_D_WU 0xfff0007f |
#define | MATCH_FCVT_D_L 0xd2200053 |
#define | MASK_FCVT_D_L 0xfff0007f |
#define | MATCH_FCVT_D_LU 0xd2300053 |
#define | MASK_FCVT_D_LU 0xfff0007f |
#define | MATCH_FMV_D_X 0xf2000053 |
#define | MASK_FMV_D_X 0xfff0707f |
#define | MATCH_FCVT_Q_W 0xd6000053 |
#define | MASK_FCVT_Q_W 0xfff0007f |
#define | MATCH_FCVT_Q_WU 0xd6100053 |
#define | MASK_FCVT_Q_WU 0xfff0007f |
#define | MATCH_FCVT_Q_L 0xd6200053 |
#define | MASK_FCVT_Q_L 0xfff0007f |
#define | MATCH_FCVT_Q_LU 0xd6300053 |
#define | MASK_FCVT_Q_LU 0xfff0007f |
#define | MATCH_FMV_Q_X 0xf6000053 |
#define | MASK_FMV_Q_X 0xfff0707f |
#define | MATCH_FLW 0x2007 |
#define | MASK_FLW 0x707f |
#define | MATCH_FLD 0x3007 |
#define | MASK_FLD 0x707f |
#define | MATCH_FLQ 0x4007 |
#define | MASK_FLQ 0x707f |
#define | MATCH_FSW 0x2027 |
#define | MASK_FSW 0x707f |
#define | MATCH_FSD 0x3027 |
#define | MASK_FSD 0x707f |
#define | MATCH_FSQ 0x4027 |
#define | MASK_FSQ 0x707f |
#define | MATCH_FMADD_S 0x43 |
#define | MASK_FMADD_S 0x600007f |
#define | MATCH_FMSUB_S 0x47 |
#define | MASK_FMSUB_S 0x600007f |
#define | MATCH_FNMSUB_S 0x4b |
#define | MASK_FNMSUB_S 0x600007f |
#define | MATCH_FNMADD_S 0x4f |
#define | MASK_FNMADD_S 0x600007f |
#define | MATCH_FMADD_D 0x2000043 |
#define | MASK_FMADD_D 0x600007f |
#define | MATCH_FMSUB_D 0x2000047 |
#define | MASK_FMSUB_D 0x600007f |
#define | MATCH_FNMSUB_D 0x200004b |
#define | MASK_FNMSUB_D 0x600007f |
#define | MATCH_FNMADD_D 0x200004f |
#define | MASK_FNMADD_D 0x600007f |
#define | MATCH_FMADD_Q 0x6000043 |
#define | MASK_FMADD_Q 0x600007f |
#define | MATCH_FMSUB_Q 0x6000047 |
#define | MASK_FMSUB_Q 0x600007f |
#define | MATCH_FNMSUB_Q 0x600004b |
#define | MASK_FNMSUB_Q 0x600007f |
#define | MATCH_FNMADD_Q 0x600004f |
#define | MASK_FNMADD_Q 0x600007f |
#define | MATCH_C_NOP 0x1 |
#define | MASK_C_NOP 0xffff |
#define | MATCH_C_ADDI16SP 0x6101 |
#define | MASK_C_ADDI16SP 0xef83 |
#define | MATCH_C_JR 0x8002 |
#define | MASK_C_JR 0xf07f |
#define | MATCH_C_JALR 0x9002 |
#define | MASK_C_JALR 0xf07f |
#define | MATCH_C_EBREAK 0x9002 |
#define | MASK_C_EBREAK 0xffff |
#define | MATCH_C_LD 0x6000 |
#define | MASK_C_LD 0xe003 |
#define | MATCH_C_SD 0xe000 |
#define | MASK_C_SD 0xe003 |
#define | MATCH_C_ADDIW 0x2001 |
#define | MASK_C_ADDIW 0xe003 |
#define | MATCH_C_LDSP 0x6002 |
#define | MASK_C_LDSP 0xe003 |
#define | MATCH_C_SDSP 0xe002 |
#define | MASK_C_SDSP 0xe003 |
#define | MATCH_C_ADDI4SPN 0x0 |
#define | MASK_C_ADDI4SPN 0xe003 |
#define | MATCH_C_FLD 0x2000 |
#define | MASK_C_FLD 0xe003 |
#define | MATCH_C_LW 0x4000 |
#define | MASK_C_LW 0xe003 |
#define | MATCH_C_FLW 0x6000 |
#define | MASK_C_FLW 0xe003 |
#define | MATCH_C_FSD 0xa000 |
#define | MASK_C_FSD 0xe003 |
#define | MATCH_C_SW 0xc000 |
#define | MASK_C_SW 0xe003 |
#define | MATCH_C_FSW 0xe000 |
#define | MASK_C_FSW 0xe003 |
#define | MATCH_C_ADDI 0x1 |
#define | MASK_C_ADDI 0xe003 |
#define | MATCH_C_JAL 0x2001 |
#define | MASK_C_JAL 0xe003 |
#define | MATCH_C_LI 0x4001 |
#define | MASK_C_LI 0xe003 |
#define | MATCH_C_LUI 0x6001 |
#define | MASK_C_LUI 0xe003 |
#define | MATCH_C_SRLI 0x8001 |
#define | MASK_C_SRLI 0xec03 |
#define | MATCH_C_SRAI 0x8401 |
#define | MASK_C_SRAI 0xec03 |
#define | MATCH_C_ANDI 0x8801 |
#define | MASK_C_ANDI 0xec03 |
#define | MATCH_C_SUB 0x8c01 |
#define | MASK_C_SUB 0xfc63 |
#define | MATCH_C_XOR 0x8c21 |
#define | MASK_C_XOR 0xfc63 |
#define | MATCH_C_OR 0x8c41 |
#define | MASK_C_OR 0xfc63 |
#define | MATCH_C_AND 0x8c61 |
#define | MASK_C_AND 0xfc63 |
#define | MATCH_C_SUBW 0x9c01 |
#define | MASK_C_SUBW 0xfc63 |
#define | MATCH_C_ADDW 0x9c21 |
#define | MASK_C_ADDW 0xfc63 |
#define | MATCH_C_J 0xa001 |
#define | MASK_C_J 0xe003 |
#define | MATCH_C_BEQZ 0xc001 |
#define | MASK_C_BEQZ 0xe003 |
#define | MATCH_C_BNEZ 0xe001 |
#define | MASK_C_BNEZ 0xe003 |
#define | MATCH_C_SLLI 0x2 |
#define | MASK_C_SLLI 0xe003 |
#define | MATCH_C_FLDSP 0x2002 |
#define | MASK_C_FLDSP 0xe003 |
#define | MATCH_C_LWSP 0x4002 |
#define | MASK_C_LWSP 0xe003 |
#define | MATCH_C_FLWSP 0x6002 |
#define | MASK_C_FLWSP 0xe003 |
#define | MATCH_C_MV 0x8002 |
#define | MASK_C_MV 0xf003 |
#define | MATCH_C_ADD 0x9002 |
#define | MASK_C_ADD 0xf003 |
#define | MATCH_C_FSDSP 0xa002 |
#define | MASK_C_FSDSP 0xe003 |
#define | MATCH_C_SWSP 0xc002 |
#define | MASK_C_SWSP 0xe003 |
#define | MATCH_C_FSWSP 0xe002 |
#define | MASK_C_FSWSP 0xe003 |
#define | MATCH_CUSTOM0 0xb |
#define | MASK_CUSTOM0 0x707f |
#define | MATCH_CUSTOM0_RS1 0x200b |
#define | MASK_CUSTOM0_RS1 0x707f |
#define | MATCH_CUSTOM0_RS1_RS2 0x300b |
#define | MASK_CUSTOM0_RS1_RS2 0x707f |
#define | MATCH_CUSTOM0_RD 0x400b |
#define | MASK_CUSTOM0_RD 0x707f |
#define | MATCH_CUSTOM0_RD_RS1 0x600b |
#define | MASK_CUSTOM0_RD_RS1 0x707f |
#define | MATCH_CUSTOM0_RD_RS1_RS2 0x700b |
#define | MASK_CUSTOM0_RD_RS1_RS2 0x707f |
#define | MATCH_CUSTOM1 0x2b |
#define | MASK_CUSTOM1 0x707f |
#define | MATCH_CUSTOM1_RS1 0x202b |
#define | MASK_CUSTOM1_RS1 0x707f |
#define | MATCH_CUSTOM1_RS1_RS2 0x302b |
#define | MASK_CUSTOM1_RS1_RS2 0x707f |
#define | MATCH_CUSTOM1_RD 0x402b |
#define | MASK_CUSTOM1_RD 0x707f |
#define | MATCH_CUSTOM1_RD_RS1 0x602b |
#define | MASK_CUSTOM1_RD_RS1 0x707f |
#define | MATCH_CUSTOM1_RD_RS1_RS2 0x702b |
#define | MASK_CUSTOM1_RD_RS1_RS2 0x707f |
#define | MATCH_CUSTOM2 0x5b |
#define | MASK_CUSTOM2 0x707f |
#define | MATCH_CUSTOM2_RS1 0x205b |
#define | MASK_CUSTOM2_RS1 0x707f |
#define | MATCH_CUSTOM2_RS1_RS2 0x305b |
#define | MASK_CUSTOM2_RS1_RS2 0x707f |
#define | MATCH_CUSTOM2_RD 0x405b |
#define | MASK_CUSTOM2_RD 0x707f |
#define | MATCH_CUSTOM2_RD_RS1 0x605b |
#define | MASK_CUSTOM2_RD_RS1 0x707f |
#define | MATCH_CUSTOM2_RD_RS1_RS2 0x705b |
#define | MASK_CUSTOM2_RD_RS1_RS2 0x707f |
#define | MATCH_CUSTOM3 0x7b |
#define | MASK_CUSTOM3 0x707f |
#define | MATCH_CUSTOM3_RS1 0x207b |
#define | MASK_CUSTOM3_RS1 0x707f |
#define | MATCH_CUSTOM3_RS1_RS2 0x307b |
#define | MASK_CUSTOM3_RS1_RS2 0x707f |
#define | MATCH_CUSTOM3_RD 0x407b |
#define | MASK_CUSTOM3_RD 0x707f |
#define | MATCH_CUSTOM3_RD_RS1 0x607b |
#define | MASK_CUSTOM3_RD_RS1 0x707f |
#define | MATCH_CUSTOM3_RD_RS1_RS2 0x707b |
#define | MASK_CUSTOM3_RD_RS1_RS2 0x707f |
#define | CSR_FFLAGS 0x1 |
#define | CSR_FRM 0x2 |
#define | CSR_FCSR 0x3 |
#define | CSR_CYCLE 0xc00 |
#define | CSR_TIME 0xc01 |
#define | CSR_INSTRET 0xc02 |
#define | CSR_HPMCOUNTER3 0xc03 |
#define | CSR_HPMCOUNTER4 0xc04 |
#define | CSR_HPMCOUNTER5 0xc05 |
#define | CSR_HPMCOUNTER6 0xc06 |
#define | CSR_HPMCOUNTER7 0xc07 |
#define | CSR_HPMCOUNTER8 0xc08 |
#define | CSR_HPMCOUNTER9 0xc09 |
#define | CSR_HPMCOUNTER10 0xc0a |
#define | CSR_HPMCOUNTER11 0xc0b |
#define | CSR_HPMCOUNTER12 0xc0c |
#define | CSR_HPMCOUNTER13 0xc0d |
#define | CSR_HPMCOUNTER14 0xc0e |
#define | CSR_HPMCOUNTER15 0xc0f |
#define | CSR_HPMCOUNTER16 0xc10 |
#define | CSR_HPMCOUNTER17 0xc11 |
#define | CSR_HPMCOUNTER18 0xc12 |
#define | CSR_HPMCOUNTER19 0xc13 |
#define | CSR_HPMCOUNTER20 0xc14 |
#define | CSR_HPMCOUNTER21 0xc15 |
#define | CSR_HPMCOUNTER22 0xc16 |
#define | CSR_HPMCOUNTER23 0xc17 |
#define | CSR_HPMCOUNTER24 0xc18 |
#define | CSR_HPMCOUNTER25 0xc19 |
#define | CSR_HPMCOUNTER26 0xc1a |
#define | CSR_HPMCOUNTER27 0xc1b |
#define | CSR_HPMCOUNTER28 0xc1c |
#define | CSR_HPMCOUNTER29 0xc1d |
#define | CSR_HPMCOUNTER30 0xc1e |
#define | CSR_HPMCOUNTER31 0xc1f |
#define | CSR_SSTATUS 0x100 |
#define | CSR_SIE 0x104 |
#define | CSR_STVEC 0x105 |
#define | CSR_SCOUNTEREN 0x106 |
#define | CSR_SSCRATCH 0x140 |
#define | CSR_SEPC 0x141 |
#define | CSR_SCAUSE 0x142 |
#define | CSR_SBADADDR 0x143 |
#define | CSR_SIP 0x144 |
#define | CSR_SPTBR 0x180 |
#define | CSR_MSTATUS 0x300 |
#define | CSR_MISA 0x301 |
#define | CSR_MEDELEG 0x302 |
#define | CSR_MIDELEG 0x303 |
#define | CSR_MIE 0x304 |
#define | CSR_MTVEC 0x305 |
#define | CSR_MCOUNTEREN 0x306 |
#define | CSR_MSCRATCH 0x340 |
#define | CSR_MEPC 0x341 |
#define | CSR_MCAUSE 0x342 |
#define | CSR_MBADADDR 0x343 |
#define | CSR_MIP 0x344 |
#define | CSR_PMPCFG0 0x3a0 |
#define | CSR_PMPCFG1 0x3a1 |
#define | CSR_PMPCFG2 0x3a2 |
#define | CSR_PMPCFG3 0x3a3 |
#define | CSR_PMPADDR0 0x3b0 |
#define | CSR_PMPADDR1 0x3b1 |
#define | CSR_PMPADDR2 0x3b2 |
#define | CSR_PMPADDR3 0x3b3 |
#define | CSR_PMPADDR4 0x3b4 |
#define | CSR_PMPADDR5 0x3b5 |
#define | CSR_PMPADDR6 0x3b6 |
#define | CSR_PMPADDR7 0x3b7 |
#define | CSR_PMPADDR8 0x3b8 |
#define | CSR_PMPADDR9 0x3b9 |
#define | CSR_PMPADDR10 0x3ba |
#define | CSR_PMPADDR11 0x3bb |
#define | CSR_PMPADDR12 0x3bc |
#define | CSR_PMPADDR13 0x3bd |
#define | CSR_PMPADDR14 0x3be |
#define | CSR_PMPADDR15 0x3bf |
#define | CSR_TSELECT 0x7a0 |
#define | CSR_TDATA1 0x7a1 |
#define | CSR_TDATA2 0x7a2 |
#define | CSR_TDATA3 0x7a3 |
#define | CSR_DCSR 0x7b0 |
#define | CSR_DPC 0x7b1 |
#define | CSR_DSCRATCH 0x7b2 |
#define | CSR_MCYCLE 0xb00 |
#define | CSR_MINSTRET 0xb02 |
#define | CSR_MHPMCOUNTER3 0xb03 |
#define | CSR_MHPMCOUNTER4 0xb04 |
#define | CSR_MHPMCOUNTER5 0xb05 |
#define | CSR_MHPMCOUNTER6 0xb06 |
#define | CSR_MHPMCOUNTER7 0xb07 |
#define | CSR_MHPMCOUNTER8 0xb08 |
#define | CSR_MHPMCOUNTER9 0xb09 |
#define | CSR_MHPMCOUNTER10 0xb0a |
#define | CSR_MHPMCOUNTER11 0xb0b |
#define | CSR_MHPMCOUNTER12 0xb0c |
#define | CSR_MHPMCOUNTER13 0xb0d |
#define | CSR_MHPMCOUNTER14 0xb0e |
#define | CSR_MHPMCOUNTER15 0xb0f |
#define | CSR_MHPMCOUNTER16 0xb10 |
#define | CSR_MHPMCOUNTER17 0xb11 |
#define | CSR_MHPMCOUNTER18 0xb12 |
#define | CSR_MHPMCOUNTER19 0xb13 |
#define | CSR_MHPMCOUNTER20 0xb14 |
#define | CSR_MHPMCOUNTER21 0xb15 |
#define | CSR_MHPMCOUNTER22 0xb16 |
#define | CSR_MHPMCOUNTER23 0xb17 |
#define | CSR_MHPMCOUNTER24 0xb18 |
#define | CSR_MHPMCOUNTER25 0xb19 |
#define | CSR_MHPMCOUNTER26 0xb1a |
#define | CSR_MHPMCOUNTER27 0xb1b |
#define | CSR_MHPMCOUNTER28 0xb1c |
#define | CSR_MHPMCOUNTER29 0xb1d |
#define | CSR_MHPMCOUNTER30 0xb1e |
#define | CSR_MHPMCOUNTER31 0xb1f |
#define | CSR_MHPMEVENT3 0x323 |
#define | CSR_MHPMEVENT4 0x324 |
#define | CSR_MHPMEVENT5 0x325 |
#define | CSR_MHPMEVENT6 0x326 |
#define | CSR_MHPMEVENT7 0x327 |
#define | CSR_MHPMEVENT8 0x328 |
#define | CSR_MHPMEVENT9 0x329 |
#define | CSR_MHPMEVENT10 0x32a |
#define | CSR_MHPMEVENT11 0x32b |
#define | CSR_MHPMEVENT12 0x32c |
#define | CSR_MHPMEVENT13 0x32d |
#define | CSR_MHPMEVENT14 0x32e |
#define | CSR_MHPMEVENT15 0x32f |
#define | CSR_MHPMEVENT16 0x330 |
#define | CSR_MHPMEVENT17 0x331 |
#define | CSR_MHPMEVENT18 0x332 |
#define | CSR_MHPMEVENT19 0x333 |
#define | CSR_MHPMEVENT20 0x334 |
#define | CSR_MHPMEVENT21 0x335 |
#define | CSR_MHPMEVENT22 0x336 |
#define | CSR_MHPMEVENT23 0x337 |
#define | CSR_MHPMEVENT24 0x338 |
#define | CSR_MHPMEVENT25 0x339 |
#define | CSR_MHPMEVENT26 0x33a |
#define | CSR_MHPMEVENT27 0x33b |
#define | CSR_MHPMEVENT28 0x33c |
#define | CSR_MHPMEVENT29 0x33d |
#define | CSR_MHPMEVENT30 0x33e |
#define | CSR_MHPMEVENT31 0x33f |
#define | CSR_MVENDORID 0xf11 |
#define | CSR_MARCHID 0xf12 |
#define | CSR_MIMPID 0xf13 |
#define | CSR_MHARTID 0xf14 |
#define | CSR_CYCLEH 0xc80 |
#define | CSR_TIMEH 0xc81 |
#define | CSR_INSTRETH 0xc82 |
#define | CSR_HPMCOUNTER3H 0xc83 |
#define | CSR_HPMCOUNTER4H 0xc84 |
#define | CSR_HPMCOUNTER5H 0xc85 |
#define | CSR_HPMCOUNTER6H 0xc86 |
#define | CSR_HPMCOUNTER7H 0xc87 |
#define | CSR_HPMCOUNTER8H 0xc88 |
#define | CSR_HPMCOUNTER9H 0xc89 |
#define | CSR_HPMCOUNTER10H 0xc8a |
#define | CSR_HPMCOUNTER11H 0xc8b |
#define | CSR_HPMCOUNTER12H 0xc8c |
#define | CSR_HPMCOUNTER13H 0xc8d |
#define | CSR_HPMCOUNTER14H 0xc8e |
#define | CSR_HPMCOUNTER15H 0xc8f |
#define | CSR_HPMCOUNTER16H 0xc90 |
#define | CSR_HPMCOUNTER17H 0xc91 |
#define | CSR_HPMCOUNTER18H 0xc92 |
#define | CSR_HPMCOUNTER19H 0xc93 |
#define | CSR_HPMCOUNTER20H 0xc94 |
#define | CSR_HPMCOUNTER21H 0xc95 |
#define | CSR_HPMCOUNTER22H 0xc96 |
#define | CSR_HPMCOUNTER23H 0xc97 |
#define | CSR_HPMCOUNTER24H 0xc98 |
#define | CSR_HPMCOUNTER25H 0xc99 |
#define | CSR_HPMCOUNTER26H 0xc9a |
#define | CSR_HPMCOUNTER27H 0xc9b |
#define | CSR_HPMCOUNTER28H 0xc9c |
#define | CSR_HPMCOUNTER29H 0xc9d |
#define | CSR_HPMCOUNTER30H 0xc9e |
#define | CSR_HPMCOUNTER31H 0xc9f |
#define | CSR_MCYCLEH 0xb80 |
#define | CSR_MINSTRETH 0xb82 |
#define | CSR_MHPMCOUNTER3H 0xb83 |
#define | CSR_MHPMCOUNTER4H 0xb84 |
#define | CSR_MHPMCOUNTER5H 0xb85 |
#define | CSR_MHPMCOUNTER6H 0xb86 |
#define | CSR_MHPMCOUNTER7H 0xb87 |
#define | CSR_MHPMCOUNTER8H 0xb88 |
#define | CSR_MHPMCOUNTER9H 0xb89 |
#define | CSR_MHPMCOUNTER10H 0xb8a |
#define | CSR_MHPMCOUNTER11H 0xb8b |
#define | CSR_MHPMCOUNTER12H 0xb8c |
#define | CSR_MHPMCOUNTER13H 0xb8d |
#define | CSR_MHPMCOUNTER14H 0xb8e |
#define | CSR_MHPMCOUNTER15H 0xb8f |
#define | CSR_MHPMCOUNTER16H 0xb90 |
#define | CSR_MHPMCOUNTER17H 0xb91 |
#define | CSR_MHPMCOUNTER18H 0xb92 |
#define | CSR_MHPMCOUNTER19H 0xb93 |
#define | CSR_MHPMCOUNTER20H 0xb94 |
#define | CSR_MHPMCOUNTER21H 0xb95 |
#define | CSR_MHPMCOUNTER22H 0xb96 |
#define | CSR_MHPMCOUNTER23H 0xb97 |
#define | CSR_MHPMCOUNTER24H 0xb98 |
#define | CSR_MHPMCOUNTER25H 0xb99 |
#define | CSR_MHPMCOUNTER26H 0xb9a |
#define | CSR_MHPMCOUNTER27H 0xb9b |
#define | CSR_MHPMCOUNTER28H 0xb9c |
#define | CSR_MHPMCOUNTER29H 0xb9d |
#define | CSR_MHPMCOUNTER30H 0xb9e |
#define | CSR_MHPMCOUNTER31H 0xb9f |
#define | CAUSE_MISALIGNED_FETCH 0x0 |
#define | CAUSE_FETCH_ACCESS 0x1 |
#define | CAUSE_ILLEGAL_INSTRUCTION 0x2 |
#define | CAUSE_BREAKPOINT 0x3 |
#define | CAUSE_MISALIGNED_LOAD 0x4 |
#define | CAUSE_LOAD_ACCESS 0x5 |
#define | CAUSE_MISALIGNED_STORE 0x6 |
#define | CAUSE_STORE_ACCESS 0x7 |
#define | CAUSE_USER_ECALL 0x8 |
#define | CAUSE_SUPERVISOR_ECALL 0x9 |
#define | CAUSE_HYPERVISOR_ECALL 0xa |
#define | CAUSE_MACHINE_ECALL 0xb |
#define | CAUSE_FETCH_PAGE_FAULT 0xc |
#define | CAUSE_LOAD_PAGE_FAULT 0xd |
#define | CAUSE_STORE_PAGE_FAULT 0xf |
RISCV utility.