RTEMS  5.0.0
reg-defs.h
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1 
9 /*
10  * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved.
11  *
12  * embedded brains GmbH
13  * Obere Lagerstr. 30
14  * 82178 Puchheim
15  * Germany
16  * <rtems@embedded-brains.de>
17  *
18  * The license and distribution terms for this file may be
19  * found in the file LICENSE in this distribution or at
20  * http://www.rtems.org/license/LICENSE.
21  */
22 
23 #ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
24 #define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
25 
26 #include <bspopts.h>
27 
28 #if MPC55XX_CHIP_FAMILY == 551
29  #define FLASH_BIUCR 0xFFFF801C
30 #else
31  #define FLASH_BIUCR 0xC3F8801C
32 #endif
33 
34 /*
35  * Definitions for FLASH_BIUCR (Flash BIU Control Register)
36  */
37 
38 /* Fields for Flash Bus Interface Control */
39 /* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */
40 
41 /* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */
42 #define FLASH_BUICR_EBI_PREFTCH 0x00080000
43 
44 /* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */
45 #define FLASH_BUICR_EDMA_PREFTCH 0x00040000
46 
47 /* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */
48 #define FLASH_BUICR_NEX_PREFTCH 0x00020000
49 
50 /* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */
51 #define FLASH_BUICR_CPU_PREFTCH 0x00010000
52 
53 /* Fields for APC (access pipelining control bits [16:18]) */
54 #define FLASH_BUICR_APC_0 0x00000000
55 #define FLASH_BUICR_APC_1 0x00002000
56 #define FLASH_BUICR_APC_2 0x00004000
57 #define FLASH_BUICR_APC_3 0x00006000
58 #define FLASH_BUICR_APC_4 0x00008000
59 #define FLASH_BUICR_APC_5 0x0000A000
60 #define FLASH_BUICR_APC_6 0x0000C000
61 #define FLASH_BUICR_APC_NO 0x0000E000
62 
63 /* Fields for WWSC (write wait state control bits [19:20]) */
64 #define FLASH_BUICR_WWSC_1 0x00000800
65 #define FLASH_BUICR_WWSC_2 0x00001000
66 #define FLASH_BUICR_WWSC_3 0x00001800
67 
68 /* Fields for RWSC (read wait state control bits [21:23]) */
69 #define FLASH_BUICR_RWSC_0 0x00000000
70 #define FLASH_BUICR_RWSC_1 0x00000100
71 #define FLASH_BUICR_RWSC_2 0x00000200
72 #define FLASH_BUICR_RWSC_3 0x00000300
73 #define FLASH_BUICR_RWSC_4 0x00000400
74 #define FLASH_BUICR_RWSC_5 0x00000500
75 #define FLASH_BUICR_RWSC_6 0x00000600
76 #define FLASH_BUICR_RWSC_7 0x00000700
77 
78 /* Fields for DPFEN (data prefetch enable bits [24:25]) */
79 #define FLASH_BUICR_DPFEN_0 0x00000000
80 #define FLASH_BUICR_DPFEN_1 0x00000040
81 #define FLASH_BUICR_DPFEN_3 0x000000C0
82 
83 /* Fields for IPFEN (instruction prefetch enable bits [26:27]) */
84 #define FLASH_BUICR_IPFEN_0 0x00000000
85 #define FLASH_BUICR_IPFEN_1 0x00000010
86 #define FLASH_BUICR_IPFEN_3 0x00000030
87 
88 /* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */
89 #define FLASH_BUICR_PFLIM_0 0x00000000
90 #define FLASH_BUICR_PFLIM_1 0x00000002
91 #define FLASH_BUICR_PFLIM_2 0x00000004
92 #define FLASH_BUICR_PFLIM_3 0x00000006
93 #define FLASH_BUICR_PFLIM_4 0x00000008
94 #define FLASH_BUICR_PFLIM_5 0x0000000A
95 #define FLASH_BUICR_PFLIM_6 0x0000000C
96 
97 /* Fields for BFEN (enable line read buffer hits bit [31]) */
98 #define FLASH_BUICR_BFEN 0x00000001
99 
100 #endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */
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