RTEMS  5.0.0
qspi.h
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29 
30 
38 #ifndef _QSPI_
39 #define _QSPI_
40 /*----------------------------------------------------------------------------
41  * Macros
42  *----------------------------------------------------------------------------*/
43 
57 #define QSPI_SCBR(baudrate, masterClock) \
58  ((uint32_t) (masterClock / baudrate) << 8)
59 
61 #define QSPI_DLYBS(delay, masterClock) \
62  ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16)
63 
65 #define QSPI_DLYBCT(delay, masterClock) \
66  ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24)
67 
68 /*--------------------------------------------------------------------------- */
69 
70 #ifdef __cplusplus
71 extern "C" {
72 #endif
73 
74 /*----------------------------------------------------------------------------
75  * Exported functions
76  *----------------------------------------------------------------------------*/
77 
80 typedef enum {
81  CmdAccess = 0,
82  ReadAccess,
83  WriteAccess
84 } Access_t;
85 
88 typedef enum {
89  SpiMode = QSPI_MR_SMM_SPI,
90  QspiMemMode = QSPI_MR_SMM_MEMORY
91 } QspiMode_t;
92 
93 
96 typedef enum {
97  ClockMode_00 = 0,
98  ClockMode_10,
99  ClockMode_01,
100  ClockMode_11
102 
103 
106 typedef enum {
107  QSPI_SUCCESS = 0,
108  QSPI_BUSY,
109  QSPI_BUSY_SENDING,
110  QSPI_READ_ERROR,
111  QSPI_WRITE_ERROR,
112  QSPI_UNKNOWN_ERROR,
113  QSPI_INIT_ERROR,
114  QSPI_INPUT_ERROR,
115  QSPI_TOTAL_ERROR
116 } QspidStatus_t;
117 
118 
121 typedef enum {
122  IsReceived = QSPI_SR_RDRF,
123  IsTxSent = QSPI_SR_TDRE,
124  IsTxEmpty = QSPI_SR_TXEMPTY,
125  IsOverrun = QSPI_SR_OVRES,
126  IsCsRise = QSPI_SR_CSR,
127  IsCsAsserted = QSPI_SR_CSS,
128  IsEofInst = QSPI_SR_INSTRE,
129  IsEnabled = QSPI_SR_QSPIENS
130 } QspiStatus_t;
131 
134 typedef struct {
135  uint8_t Instruction;
136  uint8_t Option;
137 } QspiMemCmd_t;
138 
141 typedef struct {
142  uint32_t TxDataSize; /* Tx buffer size */
143  uint32_t RxDataSize; /* Rx buffer size */
144  const void *pDataTx; /* Tx buffer */
145  void *pDataRx; /* Rx buffer */
146 } QspiBuffer_t;
147 
148 
151 typedef struct {
153  uint32_t val;
155  uint32_t bwidth: 3,
156  reserved0: 1,
157  bInstEn: 1,
158  bAddrEn: 1,
159  bOptEn: 1,
160  bDataEn: 1,
161  bOptLen: 2,
162  bAddrLen: 1,
163  reserved1: 1,
164  bXfrType: 2,
165  bContinuesRead: 1,
166  reserved2: 1,
167  bDummyCycles: 5,
168  reserved3: 11;
169  } bm;
170  } InstFrame;
171  uint32_t Addr;
173 
176 typedef struct {
177  uint8_t qspiId; /* QSPI ID */
178  Qspi *pQspiHw; /* QSPI Hw instance */
179  QspiMode_t qspiMode; /* Qspi mode: SPI or QSPI */
180  QspiMemCmd_t qspiCommand; /* Qspi command structure*/
181  QspiBuffer_t qspiBuffer; /* Qspi buffer*/
182  QspiInstFrame_t *pQspiFrame; /* Qspi QSPI mode Fram register informations*/
183 } Qspid_t;
184 
185 
186 void QSPI_SwReset(Qspi *pQspi);
187 
188 void QSPI_Disable(Qspi *pQspi);
189 
190 void QSPI_Enable(Qspi *pQspi);
191 
192 QspidStatus_t QSPI_EndTransfer(Qspi *pQspi);
193 
194 uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus);
195 
196 void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode,
197  uint32_t dwClockCfg);
198 
199 QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData);
200 
201 QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t *
202  const pData, uint32_t NumOfBytes);
203 
204 QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData);
205 
206 QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData ,
207  uint32_t NumOfBytes);
208 
209 QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources);
210 
211 QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources);
212 
213 uint32_t QSPI_GetItMask(Qspi *pQspi);
214 
215 uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi);
216 
217 QspidStatus_t QSPI_ConfigureInterface(Qspid_t *pQspid, QspiMode_t Mode,
218  uint32_t dwConfiguration);
219 
220 QspidStatus_t QSPI_SendCommand(Qspid_t *pQspi, uint8_t const KeepCfg);
221 
222 QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspi, uint8_t const KeepCfg);
223 
224 QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspi, uint8_t const KeepCfg);
225 
226 QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspi, uint8_t const KeepCfg,
227  uint8_t ScrambleFlag);
228 
229 QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite);
230 
231 #ifdef __cplusplus
232 }
233 #endif
234 
235 #endif /* #ifndef _QSPI_ */
236 
QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources)
Disables one or more interrupt sources of a QSPI peripheral.
Definition: qspi.c:275
uint32_t * pData
Definition: pio_capture.h:48
QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData, uint32_t NumOfBytes)
Sends multiple data through a SPI peripheral.
Definition: qspi.c:508
QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData)
Reads the data received by a SPI peripheral. This method must be called after a successful SPI_Write ...
Definition: qspi.c:383
QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspi, uint8_t const KeepCfg, uint8_t ScrambleFlag)
Sends an instruction over QSPI and configures other related address like Addr , Frame and synchronise...
Definition: qspi.c:695
QspidStatus_t QSPI_EndTransfer(Qspi *pQspi)
Ends ongoing transfer by releasing CS of QSPI peripheral.
Definition: qspi.c:360
QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite)
Writes or reads the QSPI memory (0x80000000) to transmit or receive data from Flash memory...
Definition: qspi.c:730
QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspi, uint8_t const KeepCfg)
Send instruction over QSPI to read data.
Definition: qspi.c:652
QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t *const pData, uint32_t NumOfBytes)
Reads multiple data received by a SPI peripheral. This method must be called after a successful SPI_W...
Definition: qspi.c:422
QspiClockMode_t
qspi clock modes , regarding clock phase and clock polarity
Definition: qspi.h:96
#define QSPI_SR_TDRE
(QSPI_SR) Transmit Data Register Empty
Definition: component_qspi.h:104
uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi)
Returns enabled interrupt status.
Definition: qspi.c:298
Access_t
qspi access modes
Definition: qspi.h:80
QspidStatus_t QSPI_ConfigureInterface(Qspid_t *pQspid, QspiMode_t Mode, uint32_t dwConfiguration)
Configures QSPI/SPI.
Definition: qspi.c:339
qspi frame structure for QSPI mode
Definition: qspi.h:151
qspi buffer structure
Definition: qspi.h:141
uint32_t reserved2
Definition: qspi.h:155
#define QSPI_SR_QSPIENS
(QSPI_SR) QSPI Enable Status
Definition: component_qspi.h:110
#define QSPI_SR_CSR
(QSPI_SR) Chip Select Rise
Definition: component_qspi.h:107
#define QSPI_SR_RDRF
(QSPI_SR) Receive Data Register Full
Definition: component_qspi.h:103
qspi command structure
Definition: qspi.h:134
void QSPI_Disable(Qspi *pQspi)
Disables a QSPI peripheral.
Definition: qspi.c:237
qspi driver structure
Definition: qspi.h:176
#define QSPI_SR_TXEMPTY
(QSPI_SR) Transmission Registers Empty
Definition: component_qspi.h:105
void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode, uint32_t dwClockCfg)
Configures peripheral clock of a QSPI/SPI peripheral.
Definition: qspi.c:324
uint32_t QSPI_GetItMask(Qspi *pQspi)
Return the interrupt mask register.
Definition: qspi.c:287
QspidStatus_t QSPI_SendCommand(Qspid_t *pQspi, uint8_t const KeepCfg)
Send an instruction over QSPI (oly a flash command no data)
Definition: qspi.c:560
QspiStatus_t
qspi status regiter bits
Definition: qspi.h:121
#define QSPI_SR_OVRES
(QSPI_SR) Overrun Error Status
Definition: component_qspi.h:106
QspidStatus_t
qspi status codes
Definition: qspi.h:106
QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspi, uint8_t const KeepCfg)
Send instruction over QSPI with data.
Definition: qspi.c:610
QspiMode_t
qspi modes SPI or QSPI
Definition: qspi.h:88
QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources)
Enables one or more interrupt sources of a QSPI peripheral.
Definition: qspi.c:262
Qspi hardware registers.
Definition: component_qspi.h:41
#define QSPI_SR_CSS
(QSPI_SR) Chip Select Status
Definition: component_qspi.h:108
uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus)
Get the current status register of the given QSPI peripheral.
Definition: qspi.c:312
void QSPI_SwReset(Qspi *pQspi)
Resets a QSPI peripheral.
Definition: qspi.c:250
#define QSPI_MR_SMM_MEMORY
(QSPI_MR) The QSPI is in Serial Memory mode.
Definition: component_qspi.h:71
QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData)
Sends a single data through a SPI peripheral.
Definition: qspi.c:473
#define QSPI_SR_INSTRE
(QSPI_SR) Instruction End Status
Definition: component_qspi.h:109
#define QSPI_MR_SMM_SPI
(QSPI_MR) The QSPI is in SPI mode.
Definition: component_qspi.h:70
Definition: qspi.h:152
void QSPI_Enable(Qspi *pQspi)
Enables a QSPI peripheral.
Definition: qspi.c:224