RTEMS  5.0.0
bsp.h
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1 
9 /*
10  * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
11  *
12  * The license and distribution terms for this file may be
13  * found in the file LICENSE in this distribution or at
14  * http://www.rtems.org/license/LICENSE.
15  *
16  * Adapted for the mvme3100 BSP by T. Straumann, 2007.
17  */
18 #ifndef LIBBSP_POWERPC_MVME3100_BSP_H
19 #define LIBBSP_POWERPC_MVME3100_BSP_H
20 
21 #ifndef ASM
22 
23 #include <bspopts.h>
24 #include <bsp/default-initial-extension.h>
25 
26 #include <rtems.h>
27 #include <libcpu/io.h>
28 #include <bsp/vectors.h>
29 
40 #define BSP_INTERRUPT_STACK_SIZE (16 * 1024)
41 
42 /*
43  * diagram illustrating the role of the configuration
44  * constants
45  * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible
46  * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this
47  * address being 'visible' or not!).
48  * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME
49  * _VME_A32_WIN0_ON_VME: VME address of that same window
50  *
51  * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between
52  * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI
53  * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to
54  * the base address read from PCI config.space in order to translate that
55  * into a CPU address.
56  *
57  * NOTE: VME addresses should NEVER be translated using these constants!
58  * they are strictly for BSP internal use. Drivers etc. should use
59  * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs).
60  *
61  * CPU ADDR PCI_ADDR VME ADDR
62  *
63  * 00000000 XXXXXXXX XXXXXXXX
64  * ^ ^ ........
65  * | |
66  * | | e.g., RAM XXXXXXXX
67  * | | 00000000
68  * | | ......... ^
69  * | | (possible offset |
70  * | | between pci and XXXXXXXX | ......
71  * | | cpu addresses) |
72  * | v |
73  * | PCI_MEM_BASE -------------> 00000000 --------------- |
74  * | ........ ........ ^ |
75  * | invisible | |
76  * | ........ from CPU | |
77  * v | |
78  * PCI_MEM_WIN0 ============= first visible PCI addr | |
79  * | |
80  * pci devices pci window | |
81  * visible here v v
82  * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME
83  * vme window
84  * VME devices hostbridge mapped by
85  * visible here universe
86  * =====================================================
87  *
88  */
89 
90 /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
91 #define _IO_BASE 0xe0000000 /* Motload's PCI IO base */
92 #define _ISA_MEM_BASE CHRP_ISA_MEM_BASE
93 /* address of our ram on the PCI bus */
94 #define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET
95 /* offset of pci memory as seen from the CPU */
96 #define PCI_MEM_BASE 0
97 /* where (in CPU addr. space) does the PCI window start */
98 #define PCI_MEM_WIN0 0x80000000
99 
100 /*
101  * Base address definitions for several devices
102  */
103 
104 #define BSP_OPEN_PIC_BASE_OFFSET 0x40000
105 #define BSP_OPEN_PIC_BIG_ENDIAN
106 
107 #define BSP_8540_CCSR_BASE (0xe1000000)
108 
109 #define BSP_UART_IOBASE_COM1 (BSP_8540_CCSR_BASE+0x4500)
110 #define BSP_UART_IOBASE_COM2 (BSP_8540_CCSR_BASE+0x4600)
111 #define PCI_CONFIG_ADDR (BSP_8540_CCSR_BASE+0x8000)
112 #define PCI_CONFIG_DATA (BSP_8540_CCSR_BASE+0x8004)
113 #define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((uint32_t*)(addr), (val))
114 
115 #define BSP_CONSOLE_PORT BSP_UART_COM1
116 #define BSP_UART_BAUD_BASE (-9600) /* use existing divisor to determine clock rate */
117 #define BSP_UART_USE_SHARED_IRQS
118 
119 #define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007)
120 
121 /* I2C Devices */
122 /* Note that the i2c addresses stated in the manual are
123  * left-shifted by one bit.
124  */
125 #define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */
126 #define BSP_USR0_I2C_ADDR (0xA4>>1) /* the 1st user EEPROM */
127 #define BSP_USR1_I2C_ADDR (0xA6>>1) /* the 2nd user EEPROM */
128 #define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */
129 #define BSP_RTC_I2C_ADDR (0xD0>>1) /* the DS1375 wall-clock */
130 
131 #define BSP_I2C_BUS_DESCRIPTOR mpc8540_i2c_bus_descriptor
132 
133 #define BSP_I2C_BUS0_NAME "/dev/i2c0"
134 
135 #define BSP_I2C_VPD_EEPROM_NAME "vpd-eeprom"
136 #define BSP_I2C_USR_EEPROM_NAME "usr-eeprom"
137 #define BSP_I2C_USR1_EEPROM_NAME "usr1-eeprom"
138 #define BSP_I2C_DS1621_NAME "ds1621"
139 #define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME
140 #define BSP_I2C_DS1621_RAW_NAME "ds1621-raw"
141 #define BSP_I2C_DS1375_RAW_NAME "ds1375-raw"
142 #define BSP_I2C_RTC_RAW_NAME BSP_I2C_DS1375_RAW_NAME
143 
144 #define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME "." BSP_I2C_VPD_EEPROM_NAME)
145 #define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME "." BSP_I2C_USR_EEPROM_NAME)
146 #define BSP_I2C_USR1_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME "." BSP_I2C_USR1_EEPROM_NAME)
147 #define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME "." BSP_I2C_DS1621_NAME)
148 #define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME
149 #define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME "." BSP_I2C_DS1621_RAW_NAME)
150 #define BSP_I2C_DS1375_RAW_DEV_NAME (BSP_I2C_BUS0_NAME "." BSP_I2C_DS1375_RAW_NAME)
151 
152 /* Definitions useful for bootloader (netboot); where to find
153  * boot/'environment' parameters.
154  */
155 #define BSP_EEPROM_BOOTPARMS_NAME BSP_I2C_USR1_EEPROM_DEV_NAME
156 #define BSP_EEPROM_BOOTPARMS_SIZE 1024
157 #define BSP_EEPROM_BOOTPARMS_OFFSET 0
158 #define BSP_BOOTPARMS_WRITE_ENABLE() do { BSP_eeprom_write_enable(); } while (0)
159 #define BSP_BOOTPARMS_WRITE_DISABLE() do { BSP_eeprom_write_protect();} while (0)
160 
161 
162 #ifdef __cplusplus
163 extern "C" {
164 #endif
165 /* Initialize the I2C driver and register all devices
166  * RETURNS 0 on success, -1 on error.
167  *
168  * Access to the VPD and user EEPROMS as well
169  * as the ds1621 temperature sensor is possible
170  * by means of file nodes
171  *
172  * /dev/i2c0.vpd-eeprom (read-only)
173  * /dev/i2c0.usr-eeprom (read-write)
174  * /dev/i2c0.usr1-eeprom (read-write)
175  * /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC)
176  * /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621)
177  * /dev/i2c0.ds1375-raw (read-write; transfer bytes to/from the ds1375)
178  *
179  */
180 int BSP_i2c_initialize(void);
181 
182 /* System Control Register */
183 #define BSP_MVME3100_SYS_CR ((volatile uint8_t *)0xe2000001)
184 #define BSP_MVME3100_SYS_CR_RESET_MSK (7<<5)
185 #define BSP_MVME3100_SYS_CR_RESET (5<<5)
186 #define BSP_MVME3100_SYS_CR_EEPROM_WP (1<<1)
187 #define BSP_MVME3100_SYS_CR_TSTAT_MSK (1<<0)
188 
189 /* LED support */
190 #define BSP_MVME3100_SYS_IND_REG ((volatile uint8_t *)0xe2000002)
191 #define BSP_LED_BRD_FAIL (1<<0)
192 #define BSP_LED_USR1 (1<<1)
193 #define BSP_LED_USR2 (1<<2)
194 #define BSP_LED_USR3 (1<<3)
195 
196 /* Flash CSR */
197 #define BSP_MVME3100_FLASH_CSR ((volatile uint8_t *)0xe2000003)
198 #define BSP_MVME3100_FLASH_CSR_FLASH_RDY (1<<0)
199 #define BSP_MVME3100_FLASH_CSR_FBT_BLK_SEL (1<<1)
200 #define BSP_MVME3100_FLASH_CSR_F_WP_HW (1<<2)
201 #define BSP_MVME3100_FLASH_CSR_F_WP_SW (1<<3)
202 #define BSP_MVME3100_FLASH_CSR_MAP_SEL (1<<4)
203 
204 /* Phy interrupt detect */
205 #define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007)
206 
207 /* Atomically set bits in a sys-register; The bits set in 'mask'
208  * are set in the register others; are left unmodified.
209  *
210  * RETURNS: old state.
211  *
212  * NOTE : since BSP_setSysReg( reg, 0 ) does not make
213  * any changes this call may be used
214  * to read the current status w/o modifying it.
215  */
216 uint8_t BSP_setSysReg(volatile uint8_t *r, uint8_t mask);
217 
218 /* Atomically clear bits in a sys-register; The bits set in 'mask'
219  * are cleared in the register; others are left unmodified.
220  *
221  * RETURNS: old state.
222  *
223  * NOTE : since BSP_clrSysReg( reg, 0 ) does not make
224  * any changes this call may be used
225  * to read the current status w/o modifying it.
226  */
227 
228 uint8_t BSP_clrSysReg(volatile uint8_t *r, uint8_t mask);
229 
230 /* Convenience wrappers around BSP_setSysReg()/BSP_clrSysReg() */
231 
232 /* Set write-protection for all EEPROM devices
233  * RETURNS: old status
234  */
235 uint8_t BSP_eeprom_write_protect(void);
236 
237 /* Disengage write-protection for all EEPROM devices
238  * RETURNS: old status
239  */
240 uint8_t BSP_eeprom_write_enable(void);
241 
242 /* Set LEDs that have their bit set in the mask
243  *
244  * RETURNS: old status.
245  *
246  * NOTE : since BSP_setLEDs( 0 ) does not make
247  * any changes this call may be used
248  * to read the current status w/o modifying it.
249  */
250 uint8_t BSP_setLEDs(uint8_t mask);
251 
252 /* Clear LEDs that have their bit set in the mask
253  *
254  * RETURNS: old status
255  *
256  * NOTE: : see above (BSP_setLEDs)
257  */
258 uint8_t BSP_clrLEDs(uint8_t mask);
259 
260 #if 0
261 #define outport_byte(port,value) outb(value,port)
262 #define outport_word(port,value) outw(value,port)
263 #define outport_long(port,value) outl(value,port)
264 
265 #define inport_byte(port,value) (value = inb(port))
266 #define inport_word(port,value) (value = inw(port))
267 #define inport_long(port,value) (value = inl(port))
268 #endif
269 
270 /*
271  * Total memory using RESIDUAL DATA
272  */
273 extern unsigned int BSP_mem_size;
274 /*
275  * PCI Bus Frequency
276  */
277 extern unsigned int BSP_bus_frequency;
278 /*
279  * processor clock frequency
280  */
281 extern unsigned int BSP_processor_frequency;
282 /*
283  * Time base divisior (how many tick for 1 second).
284  */
285 extern unsigned int BSP_time_base_divisor;
286 /*
287  * The commandline as passed from the bootloader.
288  */
289 extern char *BSP_commandline_string;
290 
291 #define BSP_Convert_decrementer( _value ) \
292  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
293 
294 extern int BSP_disconnect_clock_handler (void);
295 extern int BSP_connect_clock_handler (void);
296 
297 /* clear hostbridge errors
298  *
299  * NOTE: The routine returns always (-1) if 'enableMCP==1'
300  * [semantics needed by libbspExt] if the MCP input is not wired.
301  * It returns and clears the error bits of the PCI status register.
302  * MCP support is disabled because:
303  * a) the 2100 has no raven chip
304  * b) the raven (2300) would raise machine check interrupts
305  * on PCI config space access to empty slots.
306  */
307 extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
308 extern void BSP_motload_pci_fixup(void);
309 
310 struct rtems_bsdnet_ifconfig;
311 
312 int
313 rtems_tsec_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching);
314 
315 #define RTEMS_BSP_NETWORK_DRIVER_NAME "tse1"
316 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_tsec_attach
317 
318 /*
319  * Prototypes for methods called only from .S for dependency tracking
320  */
321 char *save_boot_params(
322  void *r3,
323  void *r4,
324  void *r5,
325  char *cmdline_start,
326  char *cmdline_end
327 );
328 void zero_bss(void);
329 
330 /*
331  * Prototypes for methods in the BSP that cross file boundaries
332  */
333 extern void BSP_vme_config(void);
334 extern void BSP_pciConfigDump_early( void );
335 
336 #ifdef __cplusplus
337 }
338 #endif
339 
340 #endif /* !ASM */
341 
344 #endif
default-initial-extension.h
DEFAULT_INITIAL_EXTENSION Support.
vectors.h
PowerPC Exceptions API.
BSP_connect_clock_handler
int BSP_connect_clock_handler(void)
Clock Tick Device Driver.
Definition: p_clock.c:37
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