RTEMS  5.0.0
pnp.h
1 /* 11/02/95 */
2 /*----------------------------------------------------------------------------*/
3 /* Plug and Play header definitions */
4 /*----------------------------------------------------------------------------*/
5 
6 /* Structure map for PnP on PowerPC Reference Platform */
7 /* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */
8 /* (or later versions) is available on Compuserve in the PLUGPLAY area. */
9 /* This code has extensions to that specification, namely new short and */
10 /* long tag types for platform dependent information */
11 
12 /* Warning: LE notation used throughout this file */
13 
14 /* For enum's: if given in hex then they are bit significant, i.e. */
15 /* only one bit is on for each enum */
16 
17 
18 #ifndef _PNP_
19 #define _PNP_
20 
21 #ifndef ASM
22 #define MAX_MEM_REGISTERS 9
23 #define MAX_IO_PORTS 20
24 #define MAX_IRQS 7
25 /*#define MAX_DMA_CHANNELS 7*/
26 
27 /* Interrupt controllers */
28 
29 #define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */
30 #define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */
31 #define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */
32 #define PNPinterrupt3 "PNP0003" /* APIC */
33 #define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */
34 
35 /* Timers */
36 
37 #define PNPtimer0 "PNP0100" /* AT Timer */
38 #define PNPtimer1 "PNP0101" /* EISA Timer */
39 #define PNPtimer2 "PNP0102" /* MCA Timer */
40 
41 /* DMA controllers */
42 
43 #define PNPdma0 "PNP0200" /* AT DMA Controller */
44 #define PNPdma1 "PNP0201" /* EISA DMA Controller */
45 #define PNPdma2 "PNP0202" /* MCA DMA Controller */
46 
47 /* start of August 15, 1994 additions */
48 /* CMOS */
49 #define PNPCMOS "IBM0009" /* CMOS */
50 
51 /* L2 Cache */
52 #define PNPL2 "IBM0007" /* L2 Cache */
53 
54 /* NVRAM */
55 #define PNPNVRAM "IBM0008" /* NVRAM */
56 
57 /* Power Management */
58 #define PNPPM "IBM0005" /* Power Management */
59 /* end of August 15, 1994 additions */
60 
61 /* Keyboards */
62 
63 #define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */
64 #define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */
65 #define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */
66 #define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */
67 #define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */
68 #define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */
69 #define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */
70 #define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */
71 
72 /* Parallel port controllers */
73 
74 #define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */
75 #define PNPparallel1 "PNP0401" /* ECP Parallel Port */
76 #define PNPepp "IBM001C" /* EPP Parallel Port */
77 
78 /* Serial port controllers */
79 
80 #define PNPserial0 "PNP0500" /* Standard PC Serial port */
81 #define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */
82 
83 /* Disk controllers */
84 
85 #define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */
86 #define PNPdisk1 "PNP0601" /* Plus Hardcard II */
87 #define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */
88 
89 /* Diskette controllers */
90 
91 #define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */
92 
93 /* Display controllers */
94 
95 #define PNPdisplay0 "PNP0900" /* VGA Compatible */
96 #define PNPdisplay1 "PNP0901" /* Video Seven VGA */
97 #define PNPdisplay2 "PNP0902" /* 8514/A Compatible */
98 #define PNPdisplay3 "PNP0903" /* Trident VGA */
99 #define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */
100 #define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */
101 #define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */
102 #define PNPdisplay7 "PNP0907" /* Western Digital VGA */
103 #define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */
104 #define PNPdisplay9 "PNP0909" /* S3 */
105 #define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */
106 #define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */
107 #define PNPdisplayC "PNP090C" /* XGA Compatible */
108 #define PNPdisplayD "PNP090D" /* ATI VGA Wonder */
109 #define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */
110 #define PNPdisplayF "PNP090F" /* Oak Technology VGA */
111 
112 /* Peripheral busses */
113 
114 #define PNPbuses0 "PNP0A00" /* ISA Bus */
115 #define PNPbuses1 "PNP0A01" /* EISA Bus */
116 #define PNPbuses2 "PNP0A02" /* MCA Bus */
117 #define PNPbuses3 "PNP0A03" /* PCI Bus */
118 #define PNPbuses4 "PNP0A04" /* VESA/VL Bus */
119 
120 /* RTC, BIOS, planar devices */
121 
122 #define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */
123 #define PNPrtc0 "PNP0B00" /* AT RTC */
124 #define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */
125 #define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */
126 #define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */
127 #define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */
128 
129 /* PCMCIA controller */
130 
131 #define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */
132 
133 /* Mice */
134 
135 #define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */
136 #define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */
137 #define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */
138 #define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */
139 #define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */
140 #define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */
141 #define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */
142 #define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */
143 #define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */
144 #define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */
145 #define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */
146 #define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */
147 
148 /* Modems */
149 
150 #define PNPmodem0 "PNP9000" /* Specific IDs TBD */
151 
152 /* Network controllers */
153 
154 #define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */
155 #define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */
156 #define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */
157 #define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */
158 #define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */
159 #define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */
160 #define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */
161 #define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */
162 
163 /* SCSI controllers */
164 
165 #define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */
166 #define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */
167 #define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/
168 #define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */
169 #define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */
170 #define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */
171 #define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */
172 
173 /* Sound/Video, Multimedia */
174 
175 #define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */
176 #define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */
177 #define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */
178 #define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */
179 #define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */
180 #define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */
181 #define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */
182 #define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */
183 
184 /* Operator Panel */
185 #define PNPopctl "IBM000B" /* Operator's panel */
186 
187 /* Service Processor */
188 #define PNPsp "IBM0011" /* IBM Service Processor */
189 #define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */
190 #define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */
191 
192 /* Memory Controller */
193 #define PNPmemctl "IBM000A" /* Memory controller */
194 
195 /* Graphics Assist */
196 #define PNPg_assist "IBM0014" /* Graphics Assist */
197 
198 /* Miscellaneous Device Controllers */
199 #define PNPtablet "IBM0019" /* IBM Tablet Controller */
200 
201 /* PNP Packet Handles */
202 
203 #define S1_Packet 0x0A /* Version resource */
204 #define S2_Packet 0x15 /* Logical DEVID (without flags) */
205 #define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */
206 #define S3_Packet 0x1C /* Compatible device ID */
207 #define S4_Packet 0x22 /* IRQ resource (without flags) */
208 #define S4_Packet_flags 0x23 /* IRQ resource (with flags) */
209 #define S5_Packet 0x2A /* DMA resource */
210 #define S6_Packet 0x30 /* Depend funct start (w/o priority) */
211 #define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */
212 #define S7_Packet 0x38 /* Depend funct end */
213 #define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */
214 #define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */
215 #define S14_Packet 0x71 /* Vendor defined */
216 #define S15_Packet 0x78 /* End of resource (w/o checksum) */
217 #define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */
218 #define L1_Packet 0x81 /* Memory range */
219 #define L1_Shadow 0x20 /* Memory is shadowable */
220 #define L1_32bit_mem 0x18 /* 32-bit memory only */
221 #define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */
222 #define L1_Decode_Hi 0x04 /* decode supports high address */
223 #define L1_Cache 0x02 /* read cacheable, write-through */
224 #define L1_Writeable 0x01 /* Memory is writeable */
225 #define L2_Packet 0x82 /* ANSI ID string */
226 #define L3_Packet 0x83 /* Unicode ID string */
227 #define L4_Packet 0x84 /* Vendor defined */
228 #define L5_Packet 0x85 /* Large I/O */
229 #define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */
230 #define END_TAG 0x78 /* End of resource */
231 #define DF_START_TAG 0x30 /* Dependent function start */
232 #define DF_START_TAG_priority 0x31 /* Dependent function start */
233 #define DF_END_TAG 0x38 /* Dependent function end */
234 #define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */
235 
236 /* Device Base Type Codes */
237 
238 typedef enum _PnP_BASE_TYPE {
239  Reserved = 0,
240  MassStorageDevice = 1,
241  NetworkInterfaceController = 2,
242  DisplayController = 3,
243  MultimediaController = 4,
244  MemoryController = 5,
245  BridgeController = 6,
246  CommunicationsDevice = 7,
247  SystemPeripheral = 8,
248  InputDevice = 9,
249  ServiceProcessor = 0x0A, /* 11/2/95 */
250  } PnP_BASE_TYPE;
251 
252 /* Device Sub Type Codes */
253 
254 typedef enum _PnP_SUB_TYPE {
255  SCSIController = 0,
256  IDEController = 1,
257  FloppyController = 2,
258  IPIController = 3,
259  OtherMassStorageController = 0x80,
260 
261  EthernetController = 0,
262  TokenRingController = 1,
263  FDDIController = 2,
264  OtherNetworkController = 0x80,
265 
266  VGAController= 0,
267  SVGAController= 1,
268  XGAController= 2,
269  OtherDisplayController = 0x80,
270 
271  VideoController = 0,
272  AudioController = 1,
273  OtherMultimediaController = 0x80,
274 
275  RAM = 0,
276  FLASH = 1,
277  OtherMemoryDevice = 0x80,
278 
279  HostProcessorBridge = 0,
280  ISABridge = 1,
281  EISABridge = 2,
282  MicroChannelBridge = 3,
283  PCIBridge = 4,
284  PCMCIABridge = 5,
285  VMEBridge = 6,
286  OtherBridgeDevice = 0x80,
287 
288  RS232Device = 0,
289  ATCompatibleParallelPort = 1,
290  OtherCommunicationsDevice = 0x80,
291 
292  ProgrammableInterruptController = 0,
293  DMAController = 1,
294  SystemTimer = 2,
295  RealTimeClock = 3,
296  L2Cache = 4,
297  NVRAM = 5,
298  PowerManagement = 6,
299  CMOS = 7,
300  OperatorPanel = 8,
301  ServiceProcessorClass1 = 9,
302  ServiceProcessorClass2 = 0xA,
303  ServiceProcessorClass3 = 0xB,
304  GraphicAssist = 0xC,
305  SystemPlanar = 0xF, /* 10/5/95 */
306  OtherSystemPeripheral = 0x80,
307 
308  KeyboardController = 0,
309  Digitizer = 1,
310  MouseController = 2,
311  TabletController = 3, /* 10/27/95 */
312  OtherInputController = 0x80,
313 
314  GeneralMemoryController = 0,
315  } PnP_SUB_TYPE;
316 
317 /* Device Interface Type Codes */
318 
319 typedef enum _PnP_INTERFACE {
320  General = 0,
321  GeneralSCSI = 0,
322  GeneralIDE = 0,
323  ATACompatible = 1,
324 
325  GeneralFloppy = 0,
326  Compatible765 = 1,
327  NS398_Floppy = 2, /* NS Super I/O wired to use index
328  register at port 398 and data
329  register at port 399 */
330  NS26E_Floppy = 3, /* Ports 26E and 26F */
331  NS15C_Floppy = 4, /* Ports 15C and 15D */
332  NS2E_Floppy = 5, /* Ports 2E and 2F */
333  CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */
334 
335  GeneralIPI = 0,
336 
337  GeneralEther = 0,
338  GeneralToken = 0,
339  GeneralFDDI = 0,
340 
341  GeneralVGA = 0,
342  GeneralSVGA = 0,
343  GeneralXGA = 0,
344 
345  GeneralVideo = 0,
346  GeneralAudio = 0,
347  CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */
348 
349  GeneralRAM = 0,
350  GeneralFLASH = 0,
351  PCIMemoryController = 0, /* PCI Config Method */
352  RS6KMemoryController = 1, /* RS6K Config Method */
353 
354  GeneralHostBridge = 0,
355  GeneralISABridge = 0,
356  GeneralEISABridge = 0,
357  GeneralMCABridge = 0,
358  GeneralPCIBridge = 0,
359  PCIBridgeDirect = 0,
360  PCIBridgeIndirect = 1,
361  PCIBridgeRS6K = 2,
362  GeneralPCMCIABridge = 0,
363  GeneralVMEBridge = 0,
364 
365  GeneralRS232 = 0,
366  COMx = 1,
367  Compatible16450 = 2,
368  Compatible16550 = 3,
369  NS398SerPort = 4, /* NS Super I/O wired to use index
370  register at port 398 and data
371  register at port 399 */
372  NS26ESerPort = 5, /* Ports 26E and 26F */
373  NS15CSerPort = 6, /* Ports 15C and 15D */
374  NS2ESerPort = 7, /* Ports 2E and 2F */
375 
376  GeneralParPort = 0,
377  LPTx = 1,
378  NS398ParPort = 2, /* NS Super I/O wired to use index
379  register at port 398 and data
380  register at port 399 */
381  NS26EParPort = 3, /* Ports 26E and 26F */
382  NS15CParPort = 4, /* Ports 15C and 15D */
383  NS2EParPort = 5, /* Ports 2E and 2F */
384 
385  GeneralPIC = 0,
386  ISA_PIC = 1,
387  EISA_PIC = 2,
388  MPIC = 3,
389  RS6K_PIC = 4,
390 
391  GeneralDMA = 0,
392  ISA_DMA = 1,
393  EISA_DMA = 2,
394 
395  GeneralTimer = 0,
396  ISA_Timer = 1,
397  EISA_Timer = 2,
398  GeneralRTC = 0,
399  ISA_RTC = 1,
400 
401  StoreThruOnly = 1,
402  StoreInEnabled = 2,
403  RS6KL2Cache = 3,
404 
405  IndirectNVRAM = 0, /* Indirectly addressed */
406  DirectNVRAM = 1, /* Memory Mapped */
407  IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */
408 
409  GeneralPowerManagement = 0,
410  EPOWPowerManagement = 1,
411  PowerControl = 2, /* d1378 */
412 
413  GeneralCMOS = 0,
414 
415  GeneralOPPanel = 0,
416  HarddiskLight = 1,
417  CDROMLight = 2,
418  PowerLight = 3,
419  KeyLock = 4,
420  ANDisplay = 5, /* AlphaNumeric Display */
421  SystemStatusLED = 6, /* 3 digit 7 segment LED */
422  CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */
423 
424  GeneralServiceProcessor = 0,
425 
426  TransferData = 1,
427  IGMC32 = 2,
428  IGMC64 = 3,
429 
430  GeneralSystemPlanar = 0, /* 10/5/95 */
431 
432  } PnP_INTERFACE;
433 
434 /* PnP resources */
435 
436 /* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
437 
438 typedef struct _SERIAL_ID {
439  unsigned char VendorID0; /* Bit(7)=0 */
440  /* Bits(6:2)=1st character in */
441  /* compressed ASCII */
442  /* Bits(1:0)=2nd character in */
443  /* compressed ASCII bits(4:3) */
444  unsigned char VendorID1; /* Bits(7:5)=2nd character in */
445  /* compressed ASCII bits(2:0) */
446  /* Bits(4:0)=3rd character in */
447  /* compressed ASCII */
448  unsigned char VendorID2; /* Product number - vendor assigned */
449  unsigned char VendorID3; /* Product number - vendor assigned */
450 
451 /* Serial number is to provide uniqueness if more than one board of same */
452 /* type is in system. Must be "FFFFFFFF" if feature not supported. */
453 
454  unsigned char Serial0; /* Unique serial number bits (7:0) */
455  unsigned char Serial1; /* Unique serial number bits (15:8) */
456  unsigned char Serial2; /* Unique serial number bits (23:16) */
457  unsigned char Serial3; /* Unique serial number bits (31:24) */
458  unsigned char Checksum;
459  } SERIAL_ID;
460 
461 typedef enum _PnPItemName {
462  Unused = 0,
463  PnPVersion = 1,
464  LogicalDevice = 2,
465  CompatibleDevice = 3,
466  IRQFormat = 4,
467  DMAFormat = 5,
468  StartDepFunc = 6,
469  EndDepFunc = 7,
470  IOPort = 8,
471  FixedIOPort = 9,
472  Res1 = 10,
473  Res2 = 11,
474  Res3 = 12,
475  SmallVendorItem = 14,
476  EndTag = 15,
477  MemoryRange = 1,
478  ANSIIdentifier = 2,
479  UnicodeIdentifier = 3,
480  LargeVendorItem = 4,
481  MemoryRange32 = 5,
482  MemoryRangeFixed32 = 6,
483  } PnPItemName;
484 
485 /* Define a bunch of access functions for the bits in the tag field */
486 
487 /* Tag type - 0 = small; 1 = large */
488 #define tag_type(t) (((t) & 0x80)>>7)
489 #define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
490 
491 /* Small item name is 4 bits - one of PnPItemName enum above */
492 #define tag_small_item_name(t) (((t) & 0x78)>>3)
493 #define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
494 
495 /* Small item count is 3 bits - count of further bytes in packet */
496 #define tag_small_count(t) ((t) & 0x07)
497 #define set_tag_count(t,v) (t = (t & 0x78) | (v))
498 
499 /* Large item name is 7 bits - one of PnPItemName enum above */
500 #define tag_large_item_name(t) ((t) & 0x7f)
501 #define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
502 
503 /* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
504 
505 typedef union _PnP_TAG_PACKET {
506  struct _S1_Pack{ /* VERSION PACKET */
507  unsigned char Tag; /* small tag = 0x0a */
508  unsigned char Version[2]; /* PnP version, Vendor version */
509  } S1_Pack;
510 
511  struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */
512  unsigned char Tag; /* small tag = 0x15 or 0x16 */
513  unsigned char DevId[4]; /* Logical device id */
514  unsigned char Flags[2]; /* bit(0) boot device; */
515  /* bit(7:1) cmd in range x31-x37 */
516  /* bit(7:0) cmd in range x28-x3f (opt)*/
517  } S2_Pack;
518 
519  struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */
520  unsigned char Tag; /* small tag = 0x1c */
521  unsigned char CompatId[4]; /* Compatible device id */
522  } S3_Pack;
523 
524  struct _S4_Pack{ /* IRQ PACKET */
525  unsigned char Tag; /* small tag = 0x22 or 0x23 */
526  unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */
527  /* bit(0) is IRQ8 ... */
528  unsigned char IRQInfo; /* optional; assume bit(0)=1; else */
529  /* bit(0) - high true edge sensitive */
530  /* bit(1) - low true edge sensitive */
531  /* bit(2) - high true level sensitive*/
532  /* bit(3) - low true level sensitive */
533  /* bit(7:4) - must be 0 */
534  } S4_Pack;
535 
536  struct _S5_Pack{ /* DMA PACKET */
537  unsigned char Tag; /* small tag = 0x2a */
538  unsigned char DMAMask; /* bit(0) is channel 0 ... */
539  unsigned char DMAInfo;
540  } S5_Pack;
541 
542  struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */
543  unsigned char Tag; /* small tag = 0x30 or 0x31 */
544  unsigned char Priority; /* Optional; if missing then x01; else*/
545  /* x00 = best possible */
546  /* x01 = acceptible */
547  /* x02 = sub-optimal but functional */
548  } S6_Pack;
549 
550  struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */
551  unsigned char Tag; /* small tag = 0x38 */
552  } S7_Pack;
553 
554  struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */
555  unsigned char Tag; /* small tag x47 */
556  unsigned char IOInfo; /* x0 = decode only bits(9:0); */
557 #define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */
558  unsigned char RangeMin[2]; /* Min base address */
559  unsigned char RangeMax[2]; /* Max base address */
560  unsigned char IOAlign; /* base alignmt, incr in 1B blocks */
561  unsigned char IONum; /* number of contiguous I/O ports */
562  } S8_Pack;
563 
564  struct _S9_Pack{ /* FIXED I/O PORT PACKET */
565  unsigned char Tag; /* small tag = 0x4b */
566  unsigned char Range[2]; /* base address 10 bits */
567  unsigned char IONum; /* number of contiguous I/O ports */
568  } S9_Pack;
569 
570  struct _S14_Pack{ /* VENDOR DEFINED PACKET */
571  unsigned char Tag; /* small tag = 0x7m m = 1-7 */
572  union _S14_Data{
573  unsigned char Data[7]; /* Vendor defined */
574  struct _S14_PPCPack{ /* Pr*p s14 pack */
575  unsigned char Type; /* 00=non-IBM */
576  unsigned char PPCData[6]; /* Vendor defined */
577  } S14_PPCPack;
578  } S14_Data;
579  } S14_Pack;
580 
581  struct _S15_Pack{ /* END PACKET */
582  unsigned char Tag; /* small tag = 0x78 or 0x79 */
583  unsigned char Check; /* optional - checksum */
584  } S15_Pack;
585 
586  struct _L1_Pack{ /* MEMORY RANGE PACKET */
587  unsigned char Tag; /* large tag = 0x81 */
588  unsigned char Count0; /* x09 */
589  unsigned char Count1; /* x00 */
590  unsigned char Data[9]; /* a variable array of bytes, */
591  /* count in tag */
592  } L1_Pack;
593 
594  struct _L2_Pack{ /* ANSI ID STRING PACKET */
595  unsigned char Tag; /* large tag = 0x82 */
596  unsigned char Count0; /* Length of string */
597  unsigned char Count1;
598  unsigned char Identifier[1]; /* a variable array of bytes, */
599  /* count in tag */
600  } L2_Pack;
601 
602  struct _L3_Pack{ /* UNICODE ID STRING PACKET */
603  unsigned char Tag; /* large tag = 0x83 */
604  unsigned char Count0; /* Length + 2 of string */
605  unsigned char Count1;
606  unsigned char Country0; /* TBD */
607  unsigned char Country1; /* TBD */
608  unsigned char Identifier[1]; /* a variable array of bytes, */
609  /* count in tag */
610  } L3_Pack;
611 
612  struct _L4_Pack{ /* VENDOR DEFINED PACKET */
613  unsigned char Tag; /* large tag = 0x84 */
614  unsigned char Count0;
615  unsigned char Count1;
616  union _L4_Data{
617  unsigned char Data[1]; /* a variable array of bytes, */
618  /* count in tag */
619  struct _L4_PPCPack{ /* Pr*p L4 packet */
620  unsigned char Type; /* 00=non-IBM */
621  unsigned char PPCData[1]; /* a variable array of bytes, */
622  /* count in tag */
623  } L4_PPCPack;
624  } L4_Data;
625  } L4_Pack;
626 
627  struct _L5_Pack{
628  unsigned char Tag; /* large tag = 0x85 */
629  unsigned char Count0; /* Count = 17 */
630  unsigned char Count1;
631  unsigned char Data[17];
632  } L5_Pack;
633 
634  struct _L6_Pack{
635  unsigned char Tag; /* large tag = 0x86 */
636  unsigned char Count0; /* Count = 9 */
637  unsigned char Count1;
638  unsigned char Data[9];
639  } L6_Pack;
640 
641  } PnP_TAG_PACKET;
642 
643 #endif /* ASM */
644 #endif /* ndef _PNP_ */
_PnP_TAG_PACKET::_L1_Pack
Definition: pnp.h:586
_PnP_TAG_PACKET::_S4_Pack
Definition: pnp.h:524
_PnP_TAG_PACKET::_S15_Pack
Definition: pnp.h:581
_PnP_TAG_PACKET::_L4_Pack
Definition: pnp.h:612
_PnP_TAG_PACKET::_S7_Pack
Definition: pnp.h:550
_PnP_TAG_PACKET::_S3_Pack
Definition: pnp.h:519
_PnP_TAG_PACKET::_S14_Pack
Definition: pnp.h:570
_PnP_TAG_PACKET
Definition: pnp.h:505
_PnP_TAG_PACKET::_L3_Pack
Definition: pnp.h:602
_PnP_TAG_PACKET::_S14_Pack::_S14_Data
Definition: pnp.h:572
_PnP_TAG_PACKET::_L4_Pack::_L4_Data::_L4_PPCPack
Definition: pnp.h:619
_PnP_TAG_PACKET::_S6_Pack
Definition: pnp.h:542
_PnP_TAG_PACKET::_L6_Pack
Definition: pnp.h:634
_PnP_TAG_PACKET::_S9_Pack
Definition: pnp.h:564
_SERIAL_ID
Definition: pnp.h:438
_PnP_TAG_PACKET::_S2_Pack
Definition: pnp.h:511
_PnP_TAG_PACKET::_L2_Pack
Definition: pnp.h:594
_PnP_TAG_PACKET::_S5_Pack
Definition: pnp.h:536
_PnP_TAG_PACKET::_L5_Pack
Definition: pnp.h:627
_PnP_TAG_PACKET::_S8_Pack
Definition: pnp.h:554
_PnP_TAG_PACKET::_L4_Pack::_L4_Data
Definition: pnp.h:616
_PnP_TAG_PACKET::_S1_Pack
Definition: pnp.h:506
_PnP_TAG_PACKET::_S14_Pack::_S14_Data::_S14_PPCPack
Definition: pnp.h:574
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