20 #ifndef _RTEMS_SCORE_NIOS2_UTILITY_H 21 #define _RTEMS_SCORE_NIOS2_UTILITY_H 23 #define NIOS2_CTLREG_INDEX_STATUS 0 24 #define NIOS2_CTLREG_INDEX_ESTATUS 1 25 #define NIOS2_CTLREG_INDEX_BSTATUS 2 26 #define NIOS2_CTLREG_INDEX_IENABLE 3 27 #define NIOS2_CTLREG_INDEX_IPENDING 4 28 #define NIOS2_CTLREG_INDEX_CPUID 5 29 #define NIOS2_CTLREG_INDEX_EXCEPTION 7 30 #define NIOS2_CTLREG_INDEX_PTEADDR 8 31 #define NIOS2_CTLREG_INDEX_TLBACC 9 32 #define NIOS2_CTLREG_INDEX_TLBMISC 10 33 #define NIOS2_CTLREG_INDEX_BADADDR 12 34 #define NIOS2_CTLREG_INDEX_CONFIG 13 35 #define NIOS2_CTLREG_INDEX_MPUBASE 14 36 #define NIOS2_CTLREG_INDEX_MPUACC 15 38 #define NIOS2_CONTEXT_OFFSET_R16 0 39 #define NIOS2_CONTEXT_OFFSET_R17 4 40 #define NIOS2_CONTEXT_OFFSET_R18 8 41 #define NIOS2_CONTEXT_OFFSET_R19 12 42 #define NIOS2_CONTEXT_OFFSET_R20 16 43 #define NIOS2_CONTEXT_OFFSET_R21 20 44 #define NIOS2_CONTEXT_OFFSET_R22 24 45 #define NIOS2_CONTEXT_OFFSET_R23 28 46 #define NIOS2_CONTEXT_OFFSET_FP 32 47 #define NIOS2_CONTEXT_OFFSET_STATUS 36 48 #define NIOS2_CONTEXT_OFFSET_SP 40 49 #define NIOS2_CONTEXT_OFFSET_RA 44 50 #define NIOS2_CONTEXT_OFFSET_THREAD_DISPATCH_DISABLED 48 51 #define NIOS2_CONTEXT_OFFSET_STACK_MPUBASE 52 52 #define NIOS2_CONTEXT_OFFSET_STACK_MPUACC 56 54 #define NIOS2_ISR_STATUS_MASK_IIC 0xfffffffe 55 #define NIOS2_ISR_STATUS_BITS_IIC 0x00000000 57 #define NIOS2_ISR_STATUS_MASK_EIC_IL 0xfffffc0f 58 #define NIOS2_ISR_STATUS_BITS_EIC_IL 0x000003f0 60 #define NIOS2_ISR_STATUS_MASK_EIC_RSIE 0xf7ffffff 61 #define NIOS2_ISR_STATUS_BITS_EIC_RSIE 0x00000000 63 #define NIOS2_STATUS_RSIE (1 << 23) 64 #define NIOS2_STATUS_NMI (1 << 22) 65 #define NIOS2_STATUS_PRS_OFFSET 16 66 #define NIOS2_STATUS_PRS_MASK (0x3f << NIOS2_STATUS_PRS_OFFSET) 67 #define NIOS2_STATUS_CRS_OFFSET 10 68 #define NIOS2_STATUS_CRS_MASK (0x3f << NIOS2_STATUS_CRS_OFFSET) 69 #define NIOS2_STATUS_IL_OFFSET 4 70 #define NIOS2_STATUS_IL_MASK (0x3f << NIOS2_STATUS_IL_OFFSET) 71 #define NIOS2_STATUS_IH (1 << 3) 72 #define NIOS2_STATUS_EH (1 << 2) 73 #define NIOS2_STATUS_U (1 << 1) 74 #define NIOS2_STATUS_PIE (1 << 0) 76 #define NIOS2_EXCEPTION_CAUSE_OFFSET 2 77 #define NIOS2_EXCEPTION_CAUSE_MASK (0x1f << NIOS2_EXCEPTION_CAUSE_OFFSET) 79 #define NIOS2_PTEADDR_PTBASE_OFFSET 22 80 #define NIOS2_PTEADDR_PTBASE_MASK (0x3ff << NIOS2_PTEADDR_PTBASE_OFFSET) 81 #define NIOS2_PTEADDR_VPN_OFFSET 2 82 #define NIOS2_PTEADDR_VPN_MASK (0xfffff << NIOS2_PTEADDR_VPN_OFFSET) 84 #define NIOS2_TLBACC_IG_OFFSET 25 85 #define NIOS2_TLBACC_IG_MASK (0x3ff << NIOS2_TLBACC_IG_OFFSET) 86 #define NIOS2_TLBACC_C (1 << 24) 87 #define NIOS2_TLBACC_R (1 << 23) 88 #define NIOS2_TLBACC_W (1 << 22) 89 #define NIOS2_TLBACC_X (1 << 21) 90 #define NIOS2_TLBACC_G (1 << 20) 91 #define NIOS2_TLBACC_PFN_OFFSET 2 92 #define NIOS2_TLBACC_PFN_MASK (0xfffff << NIOS2_TLBACC_PFN_OFFSET) 94 #define NIOS2_TLBMISC_WAY_OFFSET 20 95 #define NIOS2_TLBMISC_WAY_MASK (0xf << NIOS2_TLBMISC_WAY_OFFSET) 96 #define NIOS2_TLBMISC_RD (1 << 19) 97 #define NIOS2_TLBMISC_WE (1 << 18) 98 #define NIOS2_TLBMISC_PID_OFFSET 5 99 #define NIOS2_TLBMISC_PID_MASK (0x3fff << NIOS2_TLBMISC_PID_OFFSET) 100 #define NIOS2_TLBMISC_DBL (1 << 3) 101 #define NIOS2_TLBMISC_BAD (1 << 2) 102 #define NIOS2_TLBMISC_PERM (1 << 1) 103 #define NIOS2_TLBMISC_D (1 << 0) 105 #define NIOS2_CONFIG_ANI (1 << 1) 106 #define NIOS2_CONFIG_PE (1 << 0) 108 #define NIOS2_MPUBASE_BASE_OFFSET 6 109 #define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET) 110 #define NIOS2_MPUBASE_INDEX_OFFSET 1 113 #define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) 115 #define NIOS2_MPUBASE_D (1 << 0) 117 #define NIOS2_MPUACC_MASK_OFFSET 6 120 #define NIOS2_MPUACC_MASK_MASK (0x7fffffc0) 122 #define NIOS2_MPUACC_LIMIT_OFFSET 6 125 #define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) 127 #define NIOS2_MPUACC_C (1 << 5) 128 #define NIOS2_MPUACC_PERM_OFFSET 2 131 #define NIOS2_MPUACC_PERM_MASK (0x0000001c) 133 #define NIOS2_MPUACC_RD (1 << 1) 134 #define NIOS2_MPUACC_WR (1 << 0) 175 static inline void _Nios2_Flush_pipeline(
void )
180 static inline uint32_t _Nios2_Get_ctlreg_status(
void )
182 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_STATUS );
185 static inline void _Nios2_Set_ctlreg_status( uint32_t value )
187 __builtin_wrctl( NIOS2_CTLREG_INDEX_STATUS, (
int) value );
190 static inline uint32_t _Nios2_Get_ctlreg_estatus(
void )
192 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_ESTATUS );
195 static inline void _Nios2_Set_ctlreg_estatus( uint32_t value )
197 __builtin_wrctl( NIOS2_CTLREG_INDEX_ESTATUS, (
int) value );
200 static inline uint32_t _Nios2_Get_ctlreg_bstatus(
void )
202 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BSTATUS );
205 static inline void _Nios2_Set_ctlreg_bstatus( uint32_t value )
207 __builtin_wrctl( NIOS2_CTLREG_INDEX_BSTATUS, (
int) value );
210 static inline uint32_t _Nios2_Get_ctlreg_ienable(
void )
212 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IENABLE );
215 static inline void _Nios2_Set_ctlreg_ienable( uint32_t value )
217 __builtin_wrctl( NIOS2_CTLREG_INDEX_IENABLE, (
int) value );
220 static inline uint32_t _Nios2_Get_ctlreg_ipending(
void )
222 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IPENDING );
225 static inline uint32_t _Nios2_Get_ctlreg_cpuid(
void )
227 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CPUID );
230 static inline uint32_t _Nios2_Get_ctlreg_exception(
void )
232 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_EXCEPTION );
235 static inline uint32_t _Nios2_Get_ctlreg_pteaddr(
void )
237 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_PTEADDR );
240 static inline void _Nios2_Set_ctlreg_pteaddr( uint32_t value )
242 __builtin_wrctl( NIOS2_CTLREG_INDEX_PTEADDR, (
int) value );
245 static inline uint32_t _Nios2_Get_ctlreg_tlbacc(
void )
247 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBACC );
250 static inline void _Nios2_Set_ctlreg_tlbacc( uint32_t value )
252 __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBACC, (
int) value );
255 static inline uint32_t _Nios2_Get_ctlreg_tlbmisc(
void )
257 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBMISC );
260 static inline void _Nios2_Set_ctlreg_tlbmisc( uint32_t value )
262 __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBMISC, (
int) value );
265 static inline uint32_t _Nios2_Get_ctlreg_badaddr(
void )
267 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BADADDR );
270 static inline uint32_t _Nios2_Get_ctlreg_config(
void )
272 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CONFIG );
275 static inline void _Nios2_Set_ctlreg_config( uint32_t value )
277 __builtin_wrctl( NIOS2_CTLREG_INDEX_CONFIG, (
int) value );
280 static inline uint32_t _Nios2_Get_ctlreg_mpubase(
void )
282 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUBASE );
285 static inline void _Nios2_Set_ctlreg_mpubase( uint32_t value )
287 __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUBASE, (
int) value );
290 static inline uint32_t _Nios2_Get_ctlreg_mpuacc(
void )
292 return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUACC );
295 static inline void _Nios2_Set_ctlreg_mpuacc( uint32_t value )
297 __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUACC, (
int) value );
300 static inline uint32_t _Nios2_ISR_Get_status_mask(
void )
302 return (uint32_t) &_Nios2_ISR_Status_mask [0];
305 static inline uint32_t _Nios2_ISR_Get_status_bits(
void )
307 return (uint32_t) &_Nios2_ISR_Status_bits [0];
310 static inline bool _Nios2_Has_internal_interrupt_controller(
void )
312 return _Nios2_ISR_Get_status_mask() == NIOS2_ISR_STATUS_MASK_IIC;
315 uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status );
318 int data_address_width;
319 int instruction_address_width;
320 int data_region_size_log2;
321 int instruction_region_size_log2;
322 int data_region_count;
323 int instruction_region_count;
324 int data_index_for_stack_protection;
325 bool region_uses_limit;
326 bool enable_data_cache_for_stack;
334 NIOS2_MPU_INST_PERM_SVR_NONE_USER_NONE = 0,
335 NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE,
336 NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_EXECUTE,
337 NIOS2_MPU_DATA_PERM_SVR_NONE_USER_NONE = 0,
338 NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE,
339 NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_READONLY,
340 NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE = 4,
341 NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READONLY,
342 NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READWRITE
343 } Nios2_MPU_Region_permissions;
349 Nios2_MPU_Region_permissions perm;
356 #define NIOS2_MPU_REGION_DESC_INST( index, base, end ) \ 358 (index), (base), (end), NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, \ 359 false, false, false, true \ 362 #define NIOS2_MPU_REGION_DESC_DATA_RO( index, base, end ) \ 364 (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, \ 365 true, true, false, true \ 368 #define NIOS2_MPU_REGION_DESC_DATA_RW( index, base, end ) \ 370 (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \ 371 true, true, false, true \ 374 #define NIOS2_MPU_REGION_DESC_DATA_IO( index, base, end ) \ 376 (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \ 377 true, false, false, true \ 380 static inline int _Nios2_MPU_Get_region_count(
386 config->data_region_count
387 : config->instruction_region_count;
390 static inline bool _Nios2_MPU_Is_valid_index(
397 && index < _Nios2_MPU_Get_region_count( config, data );
400 bool _Nios2_MPU_Setup_region_registers(
407 bool _Nios2_MPU_Get_region_descriptor(
446 static inline void _Nios2_MPU_Get_region_registers(
453 uint32_t base = (uint32_t)
454 (((index << NIOS2_MPUBASE_INDEX_OFFSET) & NIOS2_MPUBASE_INDEX_MASK)
455 | (data ? NIOS2_MPUBASE_D : 0));
457 _Nios2_Set_ctlreg_mpubase( base );
458 _Nios2_Set_ctlreg_mpuacc( NIOS2_MPUACC_RD );
459 _Nios2_Flush_pipeline();
460 *mpubase = _Nios2_Get_ctlreg_mpubase() | base;
461 *mpuacc = _Nios2_Get_ctlreg_mpuacc();
464 static inline void _Nios2_MPU_Set_region_registers(
469 _Nios2_Set_ctlreg_mpubase( mpubase );
470 _Nios2_Set_ctlreg_mpuacc( mpuacc );
471 _Nios2_Flush_pipeline();
474 static inline void _Nios2_MPU_Enable(
void )
476 uint32_t config = _Nios2_Get_ctlreg_config();
478 _Nios2_Set_ctlreg_config( config | NIOS2_CONFIG_PE );
481 static inline uint32_t _Nios2_MPU_Disable(
void )
483 uint32_t config = _Nios2_Get_ctlreg_config();
484 uint32_t config_pe = NIOS2_CONFIG_PE;
486 _Nios2_Set_ctlreg_config( config & ~config_pe );
491 static inline void _Nios2_MPU_Restore( uint32_t config )
493 _Nios2_Set_ctlreg_config( config );
496 uint32_t _Nios2_MPU_Disable_protected(
void );
506 .macro NIOS2_ASM_DISABLE_INTERRUPTS new_status, current_status
507 movhi \new_status, %hiadj(_Nios2_ISR_Status_mask)
508 addi \new_status, \new_status, %lo(_Nios2_ISR_Status_mask)
509 and \new_status, \current_status, \new_status
510 ori \new_status, \new_status, %lo(_Nios2_ISR_Status_bits)
511 wrctl status, \new_status
ssize_t read(int fd, void *buffer, size_t count)
Definition: read.c:27
Definition: deflate.c:115
ssize_t write(int fd, const void *buffer, size_t count)
Definition: write.c:30
char _Nios2_ISR_Status_mask[]
This global symbol specifies the status register mask used to disable interrupts. ...
Definition: nios2-utility.h:345
Definition: nios2-utility.h:317
bool _Nios2_MPU_Add_region(const Nios2_MPU_Configuration *config, const Nios2_MPU_Region_descriptor *desc, bool force)
Adds a region according to region descriptor desc.
Definition: nios2-mpu-add-region.c:71
uint32_t _Nios2_Thread_dispatch_disabled
Nios II specific thread dispatch disabled indicator.
Definition: nios2-thread-dispatch-disabled.c:50
char _Nios2_ISR_Status_bits[]
This symbol specifies the status register bits used to disable interrupts.
struct rtems_bsdnet_ifconfig * config
Network driver configuration.
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
int _Nios2_MPU_Get_disabled_region_index(const Nios2_MPU_Configuration *config, bool data, int begin, int end)
Searches the region table part for a disabled region.
Definition: nios2-mpu-add-region.c:39