RTEMS  5.0.0
bsp.h
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1 
9 /*
10  * COPYRIGHT (c) 1989-2012.
11  * On-Line Applications Research Corporation (OAR).
12  *
13  * The license and distribution terms for this file may be
14  * found in the file LICENSE in this distribution or at
15  * http://www.rtems.org/license/LICENSE.
16  */
17 
18 #ifndef LIBBSP_MIPS_HURRICANE_BSP_H
19 #define LIBBSP_MIPS_HURRICANE_BSP_H
20 
31 #ifndef ASM
32 
33 #include <bspopts.h>
35 
36 #include <rtems.h>
37 #include <libcpu/rm5231.h>
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 extern void WriteDisplay( char * string );
44 
45 extern uint32_t mips_get_timer( void );
46 
47 #define BSP_FEATURE_IRQ_EXTENSION
48 #define BSP_SHARED_HANDLER_SUPPORT 1
49 
50 #define CPU_CLOCK_RATE_MHZ (200)
51 #define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
52 
53 /*
54  * Simple spin delay in microsecond units for device drivers.
55  * This is very dependent on the clock speed of the target.
56  *
57  * NOTE: This macro generates a warning like "integer constant out
58  * of range" which is safe to ignore. In 64 bit mode, unsigned32
59  * types are actually 64 bits long so that comparisons between
60  * unsigned32 types and pointers are valid. The warning is caused
61  * by code in the delay macro that is necessary for 64 bit mode.
62  */
63 
64 #define rtems_bsp_delay( microseconds ) \
65  { \
66  uint32_t _end_clock = \
67  mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \
68  _end_clock %= 0x100000000; /* make sure result is 32 bits */ \
69  \
70  /* handle timer overflow, if necessary */ \
71  while ( _end_clock < mips_get_timer() ); \
72  \
73  while ( _end_clock > mips_get_timer() ); \
74  }
75 
76 /* Constants */
77 
78 #define RAM_START 0
79 #define RAM_END 0x100000
80 
81 /*
82  * Prototypes for methods called from .S for dependency tracking
83  */
84 void init_tlb(void);
85 void resettlb(int i);
86 
87 #ifdef __cplusplus
88 }
89 #endif
90 
91 #endif /* !ASM */
92 
95 #endif /* __HURRICANE_BSP_h */
DEFAULT_INITIAL_EXTENSION Support.