25 #ifndef LIBBSP_M68K_MVME147S_BSP_H 26 #define LIBBSP_M68K_MVME147S_BSP_H 49 #define RAM_START 0x00007000 50 #define RAM_END 0x003e0000 51 #define DRAM_END 0x00400000 59 uint32_t dma_table_address;
60 uint32_t dma_data_address;
61 uint32_t dma_bytecount;
62 uint32_t dma_data_holding;
65 uint16_t timer1_preload;
66 uint16_t timer1_count;
67 uint16_t timer2_preload;
68 uint16_t timer2_count;
71 uint8_t timer1_int_control;
72 uint8_t timer1_control;
73 uint8_t timer2_int_control;
74 uint8_t timer2_control;
76 uint8_t acfail_int_control;
77 uint8_t watchdog_control;
79 uint8_t printer_int_control;
80 uint8_t printer_control;
82 uint8_t dma_int_control;
84 uint8_t bus_error_int_control;
86 uint8_t abort_int_control;
87 uint8_t table_address_function_code;
88 uint8_t serial_port_int_control;
89 uint8_t general_purpose_control;
90 uint8_t lan_int_control;
91 uint8_t general_purpose_status;
92 uint8_t scsi_port_int_control;
93 uint8_t slave_base_address;
94 uint8_t software_int_1_control;
95 uint8_t int_base_vector;
96 uint8_t software_int_2_control;
97 uint8_t revision_level;
100 #define pcc ((volatile struct pcc_map * const) 0xfffe1000) 106 uint8_t system_controller;
108 uint8_t vme_bus_requester;
110 uint8_t master_configuration;
112 uint8_t slave_configuration;
114 uint8_t timer_configuration;
116 uint8_t slave_address_modifier;
118 uint8_t master_address_modifier;
120 uint8_t interrupt_handler_mask;
122 uint8_t utility_interrupt_mask;
124 uint8_t utility_interrupt_vector;
126 uint8_t interrupt_request;
128 uint8_t vme_bus_status_id;
130 uint8_t bus_error_status;
132 uint8_t gcsr_base_address;
135 #define vme_lcsr ((volatile struct vme_lcsr_map * const) 0xfffe2000) 143 uint8_t board_identification;
145 uint8_t general_purpose_0;
147 uint8_t general_purpose_1;
149 uint8_t general_purpose_2;
151 uint8_t general_purpose_3;
153 uint8_t general_purpose_4;
156 #define vme_gcsr ((volatile struct vme_gcsr_map * const) 0xfffe2020) 158 #define z8530 0xfffe3001 161 #define PCC_BASE_VECTOR 0x40 162 #define SCC_VECTOR PCC_BASE_VECTOR+3 163 #define TIMER_1_VECTOR PCC_BASE_VECTOR+8 164 #define TIMER_2_VECTOR PCC_BASE_VECTOR+9 165 #define SOFT_1_VECTOR PCC_BASE_VECTOR+10 166 #define SOFT_2_VECTOR PCC_BASE_VECTOR+11 168 #define VME_BASE_VECTOR 0x50 169 #define VME_SIGLP_VECTOR VME_BASE_VECTOR+1 171 #define USE_CHANNEL_A 1 172 #define USE_CHANNEL_B 0 174 #if (USE_CHANNEL_A == 1) 175 #define CONSOLE_CONTROL 0xfffe3002 176 #define CONSOLE_DATA 0xfffe3003 177 #elif (USE_CHANNEL_B == 1) 178 #define CONSOLE_CONTROL 0xfffe3000 179 #define CONSOLE_DATA 0xfffe3001 189 #define EXTERN extern 192 extern rtems_isr_entry M68Kvec[];
201 rtems_isr_entry handler,
rtems_isr_entry set_vector(rtems_isr_entry handler, rtems_vector_number vector, int type)
Install an interrupt handler.
Definition: setvec.c:28
DEFAULT_INITIAL_EXTENSION Support.
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47