19 #define BD115200 115200 24 #define U0_PINSEL (0x00000005) 26 #define U0_PINMASK (0x0000000F) 28 #define U1_PINSEL (0x00050000) 30 #define U1_PINMASK (0x000F0000) 37 #define LCR_WORDLENTH_BIT 0 38 #define LCR_STOPBITSEL_BIT 2 39 #define LCR_PARITYENBALE_BIT 3 40 #define LCR_PARITYSEL_BIT 4 41 #define LCR_BREAKCONTROL_BIT 6 42 #define LCR_DLAB_BIT 7 52 #define ULCR_CHAR_5 (0 << 0) 54 #define ULCR_CHAR_6 (1 << 0) 56 #define ULCR_CHAR_7 (2 << 0) 58 #define ULCR_CHAR_8 (3 << 0) 60 #define ULCR_STOP_0 (0 << 2) 62 #define ULCR_STOP_1 (1 << 2) 64 #define ULCR_PAR_NO (0 << 3) 66 #define ULCR_PAR_ODD (1 << 3) 68 #define ULCR_PAR_EVEN (3 << 3) 70 #define ULCR_PAR_MARK (5 << 3) 72 #define ULCR_PAR_SPACE (7 << 3) 74 #define ULCR_BREAK_ENABLE (1 << 6) 76 #define ULCR_DLAB_ENABLE (1 << 7) 86 #define UMCR_DTR (1 << 0) 88 #define UMCR_RTS (1 << 1) 90 #define UMCR_LB (1 << 4) 100 #define ULSR_RDR (1 << 0) 102 #define ULSR_OE (1 << 1) 104 #define ULSR_PE (1 << 2) 106 #define ULSR_FE (1 << 3) 108 #define ULSR_BI (1 << 4) 110 #define ULSR_THRE (1 << 5) 112 #define ULSR_TEMT (1 << 6) 114 #define ULSR_RXFE (1 << 7) 115 #define ULSR_ERR_MASK 0x1E 125 #define UMSR_DCTS (1 << 0) 127 #define UMSR_DDSR (1 << 1) 129 #define UMSR_TERI (1 << 2) 131 #define UMSR_DDCD (1 << 3) 133 #define UMSR_CTS (1 << 4) 135 #define UMSR_DSR (1 << 5) 137 #define UMSR_RI (1 << 6) 139 #define UMSR_DCD (1 << 7) 171 #define RC_FIFO_OVERRUN_ERR 0x1 172 #define RC_OVERRUN_ERR 0x2 173 #define RC_PARITY_ERR 0x4 174 #define RC_FRAMING_ERR 0x8 175 #define RC_BREAK_IND 0x10 #define UART1
(UART1 ) Base Address
Definition: same70j19.h:533
#define UART0
(UART0 ) Base Address
Definition: same70j19.h:531