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#define | LPC_ETH_CONFIG_TX_BUF_SIZE 1518U |
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#define | DEFAULT_PHY 0 |
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#define | WATCHDOG_TIMEOUT 5 |
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#define | ETH_RX_CTRL_SIZE_MASK 0x000007ffU |
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#define | ETH_RX_CTRL_INTERRUPT 0x80000000U |
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#define | ETH_RX_STAT_RXSIZE_MASK 0x000007ffU |
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#define | ETH_RX_STAT_BYTES 0x00000100U |
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#define | ETH_RX_STAT_CONTROL_FRAME 0x00040000U |
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#define | ETH_RX_STAT_VLAN 0x00080000U |
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#define | ETH_RX_STAT_FAIL_FILTER 0x00100000U |
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#define | ETH_RX_STAT_MULTICAST 0x00200000U |
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#define | ETH_RX_STAT_BROADCAST 0x00400000U |
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#define | ETH_RX_STAT_CRC_ERROR 0x00800000U |
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#define | ETH_RX_STAT_SYMBOL_ERROR 0x01000000U |
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#define | ETH_RX_STAT_LENGTH_ERROR 0x02000000U |
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#define | ETH_RX_STAT_RANGE_ERROR 0x04000000U |
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#define | ETH_RX_STAT_ALIGNMENT_ERROR 0x08000000U |
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#define | ETH_RX_STAT_OVERRUN 0x10000000U |
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#define | ETH_RX_STAT_NO_DESCRIPTOR 0x20000000U |
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#define | ETH_RX_STAT_LAST_FLAG 0x40000000U |
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#define | ETH_RX_STAT_ERROR 0x80000000U |
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#define | ETH_TX_CTRL_SIZE_MASK 0x7ffU |
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#define | ETH_TX_CTRL_SIZE_SHIFT 0 |
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#define | ETH_TX_CTRL_OVERRIDE 0x04000000U |
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#define | ETH_TX_CTRL_HUGE 0x08000000U |
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#define | ETH_TX_CTRL_PAD 0x10000000U |
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#define | ETH_TX_CTRL_CRC 0x20000000U |
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#define | ETH_TX_CTRL_LAST 0x40000000U |
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#define | ETH_TX_CTRL_INTERRUPT 0x80000000U |
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#define | ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U |
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#define | ETH_TX_STAT_DEFER 0x02000000U |
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#define | ETH_TX_STAT_EXCESSIVE_DEFER 0x04000000U |
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#define | ETH_TX_STAT_EXCESSIVE_COLLISION 0x08000000U |
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#define | ETH_TX_STAT_LATE_COLLISION 0x10000000U |
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#define | ETH_TX_STAT_UNDERRUN 0x20000000U |
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#define | ETH_TX_STAT_NO_DESCRIPTOR 0x40000000U |
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#define | ETH_TX_STAT_ERROR 0x80000000U |
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#define | ETH_INT_RX_OVERRUN 0x00000001U |
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#define | ETH_INT_RX_ERROR 0x00000002U |
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#define | ETH_INT_RX_FINISHED 0x00000004U |
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#define | ETH_INT_RX_DONE 0x00000008U |
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#define | ETH_INT_TX_UNDERRUN 0x00000010U |
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#define | ETH_INT_TX_ERROR 0x00000020U |
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#define | ETH_INT_TX_FINISHED 0x00000040U |
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#define | ETH_INT_TX_DONE 0x00000080U |
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#define | ETH_INT_SOFT 0x00001000U |
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#define | ETH_INT_WAKEUP 0x00002000U |
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#define | ETH_RX_FIL_CTRL_ACCEPT_UNICAST 0x00000001U |
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#define | ETH_RX_FIL_CTRL_ACCEPT_BROADCAST 0x00000002U |
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#define | ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 0x00000004U |
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#define | ETH_RX_FIL_CTRL_ACCEPT_UNICAST_HASH 0x00000008U |
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#define | ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 0x00000010U |
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#define | ETH_RX_FIL_CTRL_ACCEPT_PERFECT 0x00000020U |
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#define | ETH_RX_FIL_CTRL_MAGIC_PACKET_WOL 0x00001000U |
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#define | ETH_RX_FIL_CTRL_RX_FILTER_WOL 0x00002000U |
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#define | ETH_CMD_RX_ENABLE 0x00000001U |
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#define | ETH_CMD_TX_ENABLE 0x00000002U |
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#define | ETH_CMD_REG_RESET 0x00000008U |
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#define | ETH_CMD_TX_RESET 0x00000010U |
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#define | ETH_CMD_RX_RESET 0x00000020U |
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#define | ETH_CMD_PASS_RUNT_FRAME 0x00000040U |
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#define | ETH_CMD_PASS_RX_FILTER 0X00000080U |
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#define | ETH_CMD_TX_FLOW_CONTROL 0x00000100U |
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#define | ETH_CMD_RMII 0x00000200U |
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#define | ETH_CMD_FULL_DUPLEX 0x00000400U |
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#define | ETH_STAT_RX_ACTIVE 0x00000001U |
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#define | ETH_STAT_TX_ACTIVE 0x00000002U |
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#define | ETH_MAC2_FULL_DUPLEX BSP_BIT32(8) |
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#define | ETH_SUPP_SPEED BSP_BIT32(8) |
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#define | ETH_MCFG_CLOCK_SELECT(val) BSP_FLD32(val, 2, 4) |
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#define | ETH_MCFG_RESETMIIMGMT BSP_BIT32(15) |
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#define | ETH_MCMD_READ BSP_BIT32(0) |
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#define | ETH_MCMD_SCAN BSP_BIT32(1) |
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#define | ETH_MADR_REG(val) BSP_FLD32(val, 0, 4) |
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#define | ETH_MADR_PHY(val) BSP_FLD32(val, 8, 12) |
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#define | ETH_MIND_BUSY BSP_BIT32(0) |
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#define | ETH_MIND_SCANNING BSP_BIT32(1) |
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#define | ETH_MIND_NOT_VALID BSP_BIT32(2) |
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#define | ETH_MIND_MII_LINK_FAIL BSP_BIT32(3) |
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#define | LPC_ETH_EVENT_INITIALIZE RTEMS_EVENT_1 |
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#define | LPC_ETH_EVENT_TXSTART RTEMS_EVENT_2 |
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#define | LPC_ETH_EVENT_INTERRUPT RTEMS_EVENT_3 |
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#define | LPC_ETH_EVENT_STOP RTEMS_EVENT_4 |
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#define | LPC_ETH_INTERRUPT_RECEIVE (ETH_INT_RX_ERROR | ETH_INT_RX_FINISHED | ETH_INT_RX_DONE) |
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#define | LPC_ETH_INTERRUPT_TRANSMIT (ETH_INT_TX_DONE | ETH_INT_TX_FINISHED | ETH_INT_TX_ERROR) |
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#define | LPC_ETH_RX_STAT_ERRORS |
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#define | LPC_ETH_LAST_FRAGMENT_FLAGS |
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#define | LPC_ETH_PRINTF(...) |
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#define | LPC_ETH_PRINTK(...) |
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#define | LPC_ETH_RX_DATA_OFFSET 2 |
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#define | PHY_KSZ80X1RNL 0x221550 |
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#define | PHY_DP83848 0x20005c90 |
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