RTEMS  5.0.0
leon.h
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1 
23 /*
24  * COPYRIGHT (c) 1989-1998.
25  * On-Line Applications Research Corporation (OAR).
26  *
27  * The license and distribution terms for this file may be
28  * found in the file LICENSE in this distribution or at
29  * http://www.rtems.org/license/LICENSE.
30  *
31  * Ported to LEON implementation of the SPARC by On-Line Applications
32  * Research Corporation (OAR) under contract to the European Space
33  * Agency (ESA).
34  *
35  * LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
36  * European Space Agency.
37  */
38 
39 #ifndef _INCLUDE_LEON_h
40 #define _INCLUDE_LEON_h
41 
42 #include <rtems/score/sparc.h>
43 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47 
48 /*
49  * Interrupt Sources
50  *
51  * The interrupt source numbers directly map to the trap type and to
52  * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
53  * and the Interrupt Pending Registers.
54  */
55 
56 #define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1
57 #define LEON_INTERRUPT_UART_2_RX_TX 2
58 #define LEON_INTERRUPT_UART_1_RX_TX 3
59 #define LEON_INTERRUPT_EXTERNAL_0 4
60 #define LEON_INTERRUPT_EXTERNAL_1 5
61 #define LEON_INTERRUPT_EXTERNAL_2 6
62 #define LEON_INTERRUPT_EXTERNAL_3 7
63 #define LEON_INTERRUPT_TIMER1 8
64 #define LEON_INTERRUPT_TIMER2 9
65 #define LEON_INTERRUPT_EMPTY1 10
66 #define LEON_INTERRUPT_EMPTY2 11
67 #define LEON_INTERRUPT_EMPTY3 12
68 #define LEON_INTERRUPT_EMPTY4 13
69 #define LEON_INTERRUPT_EMPTY5 14
70 #define LEON_INTERRUPT_EMPTY6 15
71 
72 #ifndef ASM
73 
74 /*
75  * Trap Types for on-chip peripherals
76  *
77  * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
78  *
79  * NOTE: The priority level for each source corresponds to the least
80  * significant nibble of the trap type.
81  */
82 
83 #define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
84 
85 #define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
86 
87 #define LEON_INT_TRAP( _trap ) \
88  ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \
89  (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) )
90 
91 /*
92  * Structure for LEON memory mapped registers.
93  *
94  * Source: Section 6.1 - On-chip registers
95  *
96  * NOTE: There is only one of these structures per CPU, its base address
97  * is 0x80000000, and the variable LEON_REG is placed there by the
98  * linkcmds file.
99  */
100 
101 typedef struct {
102  volatile unsigned int Memory_Config_1;
103  volatile unsigned int Memory_Config_2;
104  volatile unsigned int Edac_Control;
105  volatile unsigned int Failed_Address;
106  volatile unsigned int Memory_Status;
107  volatile unsigned int Cache_Control;
108  volatile unsigned int Power_Down;
109  volatile unsigned int Write_Protection_1;
110  volatile unsigned int Write_Protection_2;
111  volatile unsigned int Leon_Configuration;
112  volatile unsigned int dummy2;
113  volatile unsigned int dummy3;
114  volatile unsigned int dummy4;
115  volatile unsigned int dummy5;
116  volatile unsigned int dummy6;
117  volatile unsigned int dummy7;
118  volatile unsigned int Timer_Counter_1;
119  volatile unsigned int Timer_Reload_1;
120  volatile unsigned int Timer_Control_1;
121  volatile unsigned int Watchdog;
122  volatile unsigned int Timer_Counter_2;
123  volatile unsigned int Timer_Reload_2;
124  volatile unsigned int Timer_Control_2;
125  volatile unsigned int dummy8;
126  volatile unsigned int Scaler_Counter;
127  volatile unsigned int Scaler_Reload;
128  volatile unsigned int dummy9;
129  volatile unsigned int dummy10;
130  volatile unsigned int UART_Channel_1;
131  volatile unsigned int UART_Status_1;
132  volatile unsigned int UART_Control_1;
133  volatile unsigned int UART_Scaler_1;
134  volatile unsigned int UART_Channel_2;
135  volatile unsigned int UART_Status_2;
136  volatile unsigned int UART_Control_2;
137  volatile unsigned int UART_Scaler_2;
138  volatile unsigned int Interrupt_Mask;
139  volatile unsigned int Interrupt_Pending;
140  volatile unsigned int Interrupt_Force;
141  volatile unsigned int Interrupt_Clear;
142  volatile unsigned int PIO_Data;
143  volatile unsigned int PIO_Direction;
144  volatile unsigned int PIO_Interrupt;
145 } LEON_Register_Map;
146 
147 #endif
148 
149 /*
150  * The following constants are intended to be used ONLY in assembly
151  * language files.
152  *
153  * NOTE: The intended style of usage is to load the address of LEON REGS
154  * into a register and then use these as displacements from
155  * that register.
156  */
157 
158 #ifdef ASM
159 
160 #define LEON_REG_MEMCFG1_OFFSET 0x00
161 #define LEON_REG_MEMCFG2_OFFSET 0x04
162 #define LEON_REG_EDACCTRL_OFFSET 0x08
163 #define LEON_REG_FAILADDR_OFFSET 0x0C
164 #define LEON_REG_MEMSTATUS_OFFSET 0x10
165 #define LEON_REG_CACHECTRL_OFFSET 0x14
166 #define LEON_REG_POWERDOWN_OFFSET 0x18
167 #define LEON_REG_WRITEPROT1_OFFSET 0x1C
168 #define LEON_REG_WRITEPROT2_OFFSET 0x20
169 #define LEON_REG_LEONCONF_OFFSET 0x24
170 #define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28
171 #define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C
172 #define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30
173 #define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34
174 #define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38
175 #define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C
176 #define LEON_REG_TIMERCNT1_OFFSET 0x40
177 #define LEON_REG_TIMERLOAD1_OFFSET 0x44
178 #define LEON_REG_TIMERCTRL1_OFFSET 0x48
179 #define LEON_REG_WDOG_OFFSET 0x4C
180 #define LEON_REG_TIMERCNT2_OFFSET 0x50
181 #define LEON_REG_TIMERLOAD2_OFFSET 0x54
182 #define LEON_REG_TIMERCTRL2_OFFSET 0x58
183 #define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C
184 #define LEON_REG_SCALERCNT_OFFSET 0x60
185 #define LEON_REG_SCALER_LOAD_OFFSET 0x64
186 #define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68
187 #define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C
188 #define LEON_REG_UARTDATA1_OFFSET 0x70
189 #define LEON_REG_UARTSTATUS1_OFFSET 0x74
190 #define LEON_REG_UARTCTRL1_OFFSET 0x78
191 #define LEON_REG_UARTSCALER1_OFFSET 0x7C
192 #define LEON_REG_UARTDATA2_OFFSET 0x80
193 #define LEON_REG_UARTSTATUS2_OFFSET 0x84
194 #define LEON_REG_UARTCTRL2_OFFSET 0x88
195 #define LEON_REG_UARTSCALER2_OFFSET 0x8C
196 #define LEON_REG_IRQMASK_OFFSET 0x90
197 #define LEON_REG_IRQPEND_OFFSET 0x94
198 #define LEON_REG_IRQFORCE_OFFSET 0x98
199 #define LEON_REG_IRQCLEAR_OFFSET 0x9C
200 #define LEON_REG_PIODATA_OFFSET 0xA0
201 #define LEON_REG_PIODIR_OFFSET 0xA4
202 #define LEON_REG_PIOIRQ_OFFSET 0xA8
203 #define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4
204 #define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8
205 
206 #endif
207 
208 /*
209  * The following defines the bits in Memory Configuration Register 1.
210  */
211 
212 #define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000
213 
214 /*
215  * The following defines the bits in Memory Configuration Register 1.
216  */
217 
218 #define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00
219 
220 
221 /*
222  * The following defines the bits in the Timer Control Register.
223  */
224 
225 #define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */
226  /* 0 = hold scalar and counter */
227 #define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */
228  /* 0 = stop at 0 */
229 #define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */
230  /* 0 = no function */
231 
232 /*
233  * The following defines the bits in the UART Control Registers.
234  *
235  */
236 
237 #define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
238 
239 /*
240  * The following defines the bits in the LEON UART Status Registers.
241  */
242 
243 #define LEON_REG_UART_STATUS_CLR 0x00000000 /* Clear all status bits */
244 #define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
245 #define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
246 #define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
247 #define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
248 #define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
249 #define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
250 #define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
251 #define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
252 
253 
254 /*
255  * The following defines the bits in the LEON UART Status Registers.
256  */
257 
258 #define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
259 #define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
260 #define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
261 #define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */
262 #define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */
263 #define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */
264 #define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */
265 #define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */
266 
267 #ifndef ASM
268 
269 /*
270  * This is used to manipulate the on-chip registers.
271  *
272  * The following symbol must be defined in the linkcmds file and point
273  * to the correct location.
274  */
275 
276 extern LEON_Register_Map LEON_REG;
277 
278 static __inline__ int bsp_irq_fixup(int irq)
279 {
280  return irq;
281 }
282 
283 /*
284  * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
285  * and the Interrupt Pending Registers.
286  *
287  * NOTE: For operations which are not atomic, this code disables interrupts
288  * to guarantee there are no intervening accesses to the same register.
289  * The operations which read the register, modify the value and then
290  * store the result back are vulnerable.
291  */
292 
293 #define LEON_Clear_interrupt( _source ) \
294  do { \
295  LEON_REG.Interrupt_Clear = (1 << (_source)); \
296  } while (0)
297 
298 #define LEON_Force_interrupt( _source ) \
299  do { \
300  LEON_REG.Interrupt_Force = (1 << (_source)); \
301  } while (0)
302 
303 #define LEON_Is_interrupt_pending( _source ) \
304  (LEON_REG.Interrupt_Pending & (1 << (_source)))
305 
306 #define LEON_Is_interrupt_masked( _source ) \
307  (!(LEON_REG.Interrupt_Mask & (1 << (_source))))
308 
309 #define LEON_Mask_interrupt( _source ) \
310  do { \
311  uint32_t _level; \
312  \
313  _level = sparc_disable_interrupts(); \
314  LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \
315  sparc_enable_interrupts( _level ); \
316  } while (0)
317 
318 #define LEON_Unmask_interrupt( _source ) \
319  do { \
320  uint32_t _level; \
321  \
322  _level = sparc_disable_interrupts(); \
323  LEON_REG.Interrupt_Mask |= (1 << (_source)); \
324  sparc_enable_interrupts( _level ); \
325  } while (0)
326 
327 #define LEON_Disable_interrupt( _source, _previous ) \
328  do { \
329  uint32_t _level; \
330  uint32_t _mask = 1 << (_source); \
331  \
332  _level = sparc_disable_interrupts(); \
333  (_previous) = LEON_REG.Interrupt_Mask; \
334  LEON_REG.Interrupt_Mask = _previous & ~_mask; \
335  sparc_enable_interrupts( _level ); \
336  (_previous) &= _mask; \
337  } while (0)
338 
339 #define LEON_Restore_interrupt( _source, _previous ) \
340  do { \
341  uint32_t _level; \
342  uint32_t _mask = 1 << (_source); \
343  \
344  _level = sparc_disable_interrupts(); \
345  LEON_REG.Interrupt_Mask = \
346  (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \
347  sparc_enable_interrupts( _level ); \
348  } while (0)
349 
350 /* Make all SPARC BSPs have common macros for interrupt handling */
351 #define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source)
352 #define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source)
353 #define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source)
354 #define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source)
355 #define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source)
356 #define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source)
357 #define BSP_Disable_interrupt(_source, _previous) \
358  LEON_Disable_interrupt(_source, _prev)
359 #define BSP_Restore_interrupt(_source, _previous) \
360  LEON_Restore_interrupt(_source, _previous)
361 
362 /* Make all SPARC BSPs have common macros for interrupt handling on any CPU */
363 #define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \
364  BSP_Is_interrupt_masked(_source)
365 #define BSP_Cpu_Unmask_interrupt(_source, _cpu) \
366  BSP_Unmask_interrupt(_source)
367 #define BSP_Cpu_Mask_interrupt(_source, _cpu) \
368  BSP_Mask_interrupt(_source)
369 #define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \
370  BSP_Disable_interrupt(_source, _prev)
371 #define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \
372  BSP_Cpu_Restore_interrupt(_source, _previous)
373 
374 /*
375  * Each timer control register is organized as follows:
376  *
377  * D0 - Enable
378  * 1 = enable counting
379  * 0 = hold scaler and counter
380  *
381  * D1 - Counter Reload
382  * 1 = reload counter at zero and restart
383  * 0 = stop counter at zero
384  *
385  * D2 - Counter Load
386  * 1 = load counter with preset value
387  * 0 = no function
388  *
389  */
390 
391 #define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002
392 #define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000
393 
394 #define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004
395 
396 #define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001
397 #define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000
398 
399 #define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002
400 #define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001
401 
402 #define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003
403 #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003
404 
405 /* Load 32-bit word by forcing a cache-miss */
406 static inline unsigned int leon_r32_no_cache(uintptr_t addr)
407 {
408  unsigned int tmp;
409  __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr));
410  return tmp;
411 }
412 
413 #endif /* !ASM */
414 
415 #ifdef __cplusplus
416 }
417 #endif
418 
419 #endif /* !_INCLUDE_LEON_h */
420 
LEON_Register_Map
Definition: leon.h:101
__asm__
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
sparc.h
Information Required to Build RTEMS for a Particular Member of the SPARC Family.
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