39 #ifndef __ALTERA_ALT_QSPI_H__ 40 #define __ALTERA_ALT_QSPI_H__ 101 #define ALT_QSPI_CFG_EN_E_DIS 0x0 107 #define ALT_QSPI_CFG_EN_E_EN 0x1 110 #define ALT_QSPI_CFG_EN_LSB 0 112 #define ALT_QSPI_CFG_EN_MSB 0 114 #define ALT_QSPI_CFG_EN_WIDTH 1 116 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001 118 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe 120 #define ALT_QSPI_CFG_EN_RESET 0x0 122 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0) 124 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001) 146 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1 152 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0 155 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1 157 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1 159 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1 161 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002 163 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd 165 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0 167 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1) 169 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002) 192 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0 198 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1 201 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2 203 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2 205 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1 207 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004 209 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb 211 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0 213 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2) 215 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004) 240 #define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0 246 #define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1 249 #define ALT_QSPI_CFG_ENDIRACC_LSB 7 251 #define ALT_QSPI_CFG_ENDIRACC_MSB 7 253 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1 255 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080 257 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f 259 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0 261 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7) 263 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080) 290 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1 296 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0 299 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8 301 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8 303 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1 305 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100 307 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff 309 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0 311 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8) 313 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100) 336 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1 342 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0 345 #define ALT_QSPI_CFG_PERSELDEC_LSB 9 347 #define ALT_QSPI_CFG_PERSELDEC_MSB 9 349 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1 351 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200 353 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff 355 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0 357 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9) 359 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200) 373 #define ALT_QSPI_CFG_PERCSLINES_LSB 10 375 #define ALT_QSPI_CFG_PERCSLINES_MSB 13 377 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4 379 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00 381 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff 383 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0 385 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10) 387 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00) 411 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1 417 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0 420 #define ALT_QSPI_CFG_WP_LSB 14 422 #define ALT_QSPI_CFG_WP_MSB 14 424 #define ALT_QSPI_CFG_WP_WIDTH 1 426 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000 428 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff 430 #define ALT_QSPI_CFG_WP_RESET 0x0 432 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14) 434 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000) 457 #define ALT_QSPI_CFG_ENDMA_E_EN 0x1 463 #define ALT_QSPI_CFG_ENDMA_E_DIS 0x0 466 #define ALT_QSPI_CFG_ENDMA_LSB 15 468 #define ALT_QSPI_CFG_ENDMA_MSB 15 470 #define ALT_QSPI_CFG_ENDMA_WIDTH 1 472 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000 474 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff 476 #define ALT_QSPI_CFG_ENDMA_RESET 0x0 478 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15) 480 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000) 504 #define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1 510 #define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0 513 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16 515 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16 517 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1 519 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000 521 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff 523 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0 525 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16) 527 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000) 559 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1 565 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0 568 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17 570 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17 572 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1 574 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000 576 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff 578 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0 580 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17) 582 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000) 614 #define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1 620 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0 623 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18 625 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18 627 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1 629 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000 631 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff 633 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0 635 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18) 637 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000) 673 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0 679 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1 685 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2 691 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3 697 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4 703 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5 709 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6 715 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7 721 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8 727 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9 733 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa 739 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb 745 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc 751 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd 757 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe 763 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf 766 #define ALT_QSPI_CFG_BAUDDIV_LSB 19 768 #define ALT_QSPI_CFG_BAUDDIV_MSB 22 770 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4 772 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000 774 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff 776 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf 778 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19) 780 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000) 803 #define ALT_QSPI_CFG_IDLE_E_SET 0x1 809 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0 812 #define ALT_QSPI_CFG_IDLE_LSB 31 814 #define ALT_QSPI_CFG_IDLE_MSB 31 816 #define ALT_QSPI_CFG_IDLE_WIDTH 1 818 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000 820 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff 822 #define ALT_QSPI_CFG_IDLE_RESET 0x0 824 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31) 826 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000) 842 uint32_t selclkpol : 1;
843 uint32_t selclkphase : 1;
845 uint32_t endiracc : 1;
846 uint32_t enlegacyip : 1;
847 uint32_t perseldec : 1;
848 uint32_t percslines : 4;
851 uint32_t enahbremap : 1;
852 uint32_t enterxipnextrd : 1;
853 uint32_t enterxipimm : 1;
854 uint32_t bauddiv : 4;
856 const uint32_t idle : 1;
864 #define ALT_QSPI_CFG_OFST 0x0 906 #define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 912 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb 915 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0 917 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7 919 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 921 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff 923 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 925 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 927 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0) 929 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff) 958 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 965 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 972 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 975 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 977 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 979 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 981 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 983 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff 985 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 987 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8) 989 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300) 1021 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 1029 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 1037 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 1040 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 1042 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 1044 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 1046 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 1048 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff 1050 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 1052 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) 1054 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) 1086 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 1094 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 1102 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 1105 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 1107 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 1109 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 1111 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 1113 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff 1115 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 1117 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) 1119 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) 1142 #define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 1148 #define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 1151 #define ALT_QSPI_DEVRD_ENMODBITS_LSB 20 1153 #define ALT_QSPI_DEVRD_ENMODBITS_MSB 20 1155 #define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 1157 #define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 1159 #define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff 1161 #define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 1163 #define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20) 1165 #define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000) 1176 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 1178 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 1180 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 1182 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 1184 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff 1186 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 1188 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24) 1190 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000) 1192 #ifndef __ASSEMBLY__ 1205 uint32_t rdopcode : 8;
1206 uint32_t instwidth : 2;
1208 uint32_t addrwidth : 2;
1210 uint32_t datawidth : 2;
1212 uint32_t enmodebits : 1;
1214 uint32_t dummyrdclks : 5;
1223 #define ALT_QSPI_DEVRD_OFST 0x4 1251 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0 1253 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7 1255 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 1257 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff 1259 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 1261 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 1263 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0) 1265 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff) 1297 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 1305 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 1313 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 1316 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 1318 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 1320 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 1322 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 1324 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff 1326 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 1328 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) 1330 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) 1362 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 1370 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 1378 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 1381 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 1383 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 1385 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 1387 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 1389 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff 1391 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 1393 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) 1395 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) 1406 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 1408 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 1410 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 1412 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 1414 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff 1416 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 1418 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24) 1420 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000) 1422 #ifndef __ASSEMBLY__ 1435 uint32_t wropcode : 8;
1437 uint32_t addrwidth : 2;
1439 uint32_t datawidth : 2;
1441 uint32_t dummywrclks : 5;
1450 #define ALT_QSPI_DEVWR_OFST 0x8 1478 #define ALT_QSPI_DELAY_INIT_LSB 0 1480 #define ALT_QSPI_DELAY_INIT_MSB 7 1482 #define ALT_QSPI_DELAY_INIT_WIDTH 8 1484 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff 1486 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 1488 #define ALT_QSPI_DELAY_INIT_RESET 0x0 1490 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0) 1492 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff) 1506 #define ALT_QSPI_DELAY_AFTER_LSB 8 1508 #define ALT_QSPI_DELAY_AFTER_MSB 15 1510 #define ALT_QSPI_DELAY_AFTER_WIDTH 8 1512 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 1514 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff 1516 #define ALT_QSPI_DELAY_AFTER_RESET 0x0 1518 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8) 1520 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00) 1533 #define ALT_QSPI_DELAY_BTWN_LSB 16 1535 #define ALT_QSPI_DELAY_BTWN_MSB 23 1537 #define ALT_QSPI_DELAY_BTWN_WIDTH 8 1539 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 1541 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff 1543 #define ALT_QSPI_DELAY_BTWN_RESET 0x0 1545 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16) 1547 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000) 1561 #define ALT_QSPI_DELAY_NSS_LSB 24 1563 #define ALT_QSPI_DELAY_NSS_MSB 31 1565 #define ALT_QSPI_DELAY_NSS_WIDTH 8 1567 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 1569 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff 1571 #define ALT_QSPI_DELAY_NSS_RESET 0x0 1573 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24) 1575 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000) 1577 #ifndef __ASSEMBLY__ 1601 #define ALT_QSPI_DELAY_OFST 0xc 1635 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0 1641 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1 1644 #define ALT_QSPI_RDDATACAP_BYP_LSB 0 1646 #define ALT_QSPI_RDDATACAP_BYP_MSB 0 1648 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1 1650 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001 1652 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe 1654 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1 1656 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0) 1658 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001) 1669 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1 1671 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4 1673 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4 1675 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e 1677 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1 1679 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0 1681 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1) 1683 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e) 1685 #ifndef __ASSEMBLY__ 1708 #define ALT_QSPI_RDDATACAP_OFST 0x10 1732 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0 1734 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3 1736 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4 1738 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f 1740 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0 1742 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2 1744 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0) 1746 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f) 1758 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4 1760 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15 1762 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12 1764 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0 1766 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f 1768 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100 1770 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4) 1772 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0) 1785 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16 1787 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20 1789 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5 1791 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000 1793 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff 1795 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10 1797 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16) 1799 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000) 1801 #ifndef __ASSEMBLY__ 1814 uint32_t numaddrbytes : 4;
1815 uint32_t bytesperdevicepage : 12;
1816 uint32_t bytespersubsector : 5;
1825 #define ALT_QSPI_DEVSZ_OFST 0x14 1849 #define ALT_QSPI_SRAMPART_ADDR_LSB 0 1851 #define ALT_QSPI_SRAMPART_ADDR_MSB 6 1853 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 7 1855 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f 1857 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80 1859 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x40 1861 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0) 1863 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f) 1865 #ifndef __ASSEMBLY__ 1887 #define ALT_QSPI_SRAMPART_OFST 0x18 1911 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0 1913 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31 1915 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32 1917 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff 1919 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000 1921 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0 1923 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0) 1925 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff) 1927 #ifndef __ASSEMBLY__ 1948 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c 1975 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0 1977 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3 1979 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4 1981 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f 1983 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0 1985 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0 1987 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0) 1989 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f) 2003 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8 2005 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11 2007 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4 2009 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00 2011 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff 2013 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0 2015 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8) 2017 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00) 2019 #ifndef __ASSEMBLY__ 2032 uint32_t numsglreqbytes : 4;
2034 uint32_t numburstreqbytes : 4;
2043 #define ALT_QSPI_DMAPER_OFST 0x20 2068 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0 2070 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31 2072 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32 2074 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff 2076 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000 2078 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0 2080 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) 2082 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) 2084 #ifndef __ASSEMBLY__ 2097 uint32_t value : 32;
2105 #define ALT_QSPI_REMAPADDR_OFST 0x24 2128 #define ALT_QSPI_MODBIT_MOD_LSB 0 2130 #define ALT_QSPI_MODBIT_MOD_MSB 7 2132 #define ALT_QSPI_MODBIT_MOD_WIDTH 8 2134 #define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff 2136 #define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00 2138 #define ALT_QSPI_MODBIT_MOD_RESET 0x0 2140 #define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0) 2142 #define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff) 2144 #ifndef __ASSEMBLY__ 2166 #define ALT_QSPI_MODBIT_OFST 0x28 2186 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0 2188 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15 2190 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16 2192 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff 2194 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000 2196 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0 2198 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0) 2200 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff) 2209 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16 2211 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31 2213 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16 2215 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000 2217 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff 2219 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0 2221 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16) 2223 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000) 2225 #ifndef __ASSEMBLY__ 2238 const uint32_t indrdpart : 16;
2239 const uint32_t indwrpart : 16;
2247 #define ALT_QSPI_SRAMFILL_OFST 0x2c 2269 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0 2271 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3 2273 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4 2275 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f 2277 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0 2279 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1 2281 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) 2283 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) 2285 #ifndef __ASSEMBLY__ 2307 #define ALT_QSPI_TXTHRESH_OFST 0x30 2331 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0 2333 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3 2335 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4 2337 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f 2339 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0 2341 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1 2343 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) 2345 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) 2347 #ifndef __ASSEMBLY__ 2369 #define ALT_QSPI_RXTHRESH_OFST 0x34 2423 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 2429 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 2432 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 2434 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 2436 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 2438 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 2440 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd 2442 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 2444 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) 2446 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) 2468 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 2474 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 2477 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 2479 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 2481 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 2483 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 2485 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb 2487 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 2489 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) 2491 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) 2514 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 2520 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 2523 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 2525 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 2527 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 2529 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 2531 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 2533 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 2535 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) 2537 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) 2559 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 2565 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 2568 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 2570 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 2572 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 2574 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 2576 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef 2578 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 2580 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) 2582 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) 2605 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 2611 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 2614 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 2616 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 2618 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 2620 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 2622 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf 2624 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 2626 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) 2628 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) 2650 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 2656 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 2659 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 2661 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 2663 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 2665 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 2667 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf 2669 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 2671 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) 2673 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) 2699 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 2705 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 2708 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7 2710 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7 2712 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 2714 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 2716 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f 2718 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 2720 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7) 2722 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080) 2745 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 2751 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 2754 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 2756 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 2758 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 2760 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 2762 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff 2764 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 2766 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) 2768 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) 2791 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 2797 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 2800 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9 2802 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9 2804 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 2806 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 2808 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff 2810 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 2812 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9) 2814 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200) 2837 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 2843 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 2846 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 2848 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 2850 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 2852 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 2854 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff 2856 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 2858 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) 2860 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) 2883 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 2889 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 2892 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11 2894 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11 2896 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 2898 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 2900 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff 2902 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 2904 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11) 2906 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800) 2929 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 2935 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 2938 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 2940 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 2942 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 2944 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 2946 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff 2948 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 2950 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) 2952 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) 2954 #ifndef __ASSEMBLY__ 2968 uint32_t underflowdet : 1;
2969 uint32_t indopdone : 1;
2970 uint32_t indrdreject : 1;
2971 uint32_t protwrattempt : 1;
2972 uint32_t illegalacc : 1;
2973 uint32_t indxfrlvl : 1;
2974 uint32_t rxover : 1;
2975 uint32_t txthreshcmp : 1;
2976 uint32_t txfull : 1;
2977 uint32_t rxthreshcmp : 1;
2978 uint32_t rxfull : 1;
2979 uint32_t indsramfull : 1;
2988 #define ALT_QSPI_IRQSTAT_OFST 0x40 3035 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0 3041 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1 3044 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1 3046 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1 3048 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1 3050 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002 3052 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd 3054 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0 3056 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) 3058 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) 3078 #define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0 3084 #define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1 3087 #define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2 3089 #define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2 3091 #define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1 3093 #define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004 3095 #define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb 3097 #define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0 3099 #define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) 3101 #define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) 3121 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0 3127 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1 3130 #define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3 3132 #define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3 3134 #define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1 3136 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008 3138 #define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7 3140 #define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0 3142 #define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) 3144 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) 3164 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0 3170 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1 3173 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4 3175 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4 3177 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1 3179 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010 3181 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef 3183 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0 3185 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) 3187 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) 3207 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0 3213 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1 3216 #define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5 3218 #define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5 3220 #define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1 3222 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020 3224 #define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf 3226 #define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0 3228 #define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) 3230 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) 3250 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0 3256 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1 3259 #define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6 3261 #define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6 3263 #define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1 3265 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040 3267 #define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf 3269 #define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0 3271 #define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) 3273 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) 3293 #define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0 3299 #define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1 3302 #define ALT_QSPI_IRQMSK_RXOVER_LSB 7 3304 #define ALT_QSPI_IRQMSK_RXOVER_MSB 7 3306 #define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1 3308 #define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080 3310 #define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f 3312 #define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0 3314 #define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7) 3316 #define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080) 3336 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0 3342 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1 3345 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8 3347 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8 3349 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1 3351 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100 3353 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff 3355 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0 3357 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) 3359 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) 3379 #define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0 3385 #define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1 3388 #define ALT_QSPI_IRQMSK_TXFULL_LSB 9 3390 #define ALT_QSPI_IRQMSK_TXFULL_MSB 9 3392 #define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1 3394 #define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200 3396 #define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff 3398 #define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0 3400 #define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9) 3402 #define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200) 3422 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0 3428 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1 3431 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10 3433 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10 3435 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1 3437 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400 3439 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff 3441 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0 3443 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) 3445 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) 3465 #define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0 3471 #define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1 3474 #define ALT_QSPI_IRQMSK_RXFULL_LSB 11 3476 #define ALT_QSPI_IRQMSK_RXFULL_MSB 11 3478 #define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1 3480 #define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800 3482 #define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff 3484 #define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0 3486 #define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11) 3488 #define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800) 3508 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0 3514 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1 3517 #define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12 3519 #define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12 3521 #define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1 3523 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000 3525 #define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff 3527 #define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0 3529 #define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) 3531 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) 3533 #ifndef __ASSEMBLY__ 3547 uint32_t underflowdet : 1;
3548 uint32_t indopdone : 1;
3549 uint32_t indrdreject : 1;
3550 uint32_t protwrattempt : 1;
3551 uint32_t illegalacc : 1;
3552 uint32_t indxfrlvl : 1;
3553 uint32_t rxover : 1;
3554 uint32_t txthreshcmp : 1;
3555 uint32_t txfull : 1;
3556 uint32_t rxthreshcmp : 1;
3557 uint32_t rxfull : 1;
3558 uint32_t indsramfull : 1;
3567 #define ALT_QSPI_IRQMSK_OFST 0x44 3590 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0 3592 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31 3594 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32 3596 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff 3598 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000 3600 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0 3602 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) 3604 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) 3606 #ifndef __ASSEMBLY__ 3619 uint32_t subsector : 32;
3627 #define ALT_QSPI_LOWWRPROT_OFST 0x50 3650 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0 3652 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31 3654 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32 3656 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff 3658 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000 3660 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0 3662 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) 3664 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) 3666 #ifndef __ASSEMBLY__ 3679 uint32_t subsector : 32;
3687 #define ALT_QSPI_UPPWRPROT_OFST 0x54 3725 #define ALT_QSPI_WRPROT_INV_E_EN 0x1 3731 #define ALT_QSPI_WRPROT_INV_E_DIS 0x0 3734 #define ALT_QSPI_WRPROT_INV_LSB 0 3736 #define ALT_QSPI_WRPROT_INV_MSB 0 3738 #define ALT_QSPI_WRPROT_INV_WIDTH 1 3740 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001 3742 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe 3744 #define ALT_QSPI_WRPROT_INV_RESET 0x0 3746 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0) 3748 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001) 3773 #define ALT_QSPI_WRPROT_EN_E_EN 0x1 3779 #define ALT_QSPI_WRPROT_EN_E_DIS 0x0 3782 #define ALT_QSPI_WRPROT_EN_LSB 1 3784 #define ALT_QSPI_WRPROT_EN_MSB 1 3786 #define ALT_QSPI_WRPROT_EN_WIDTH 1 3788 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002 3790 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd 3792 #define ALT_QSPI_WRPROT_EN_RESET 0x0 3794 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1) 3796 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002) 3798 #ifndef __ASSEMBLY__ 3821 #define ALT_QSPI_WRPROT_OFST 0x58 3862 #define ALT_QSPI_INDRD_START_E_END 0x1 3868 #define ALT_QSPI_INDRD_START_E_DISD 0x0 3871 #define ALT_QSPI_INDRD_START_LSB 0 3873 #define ALT_QSPI_INDRD_START_MSB 0 3875 #define ALT_QSPI_INDRD_START_WIDTH 1 3877 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001 3879 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe 3881 #define ALT_QSPI_INDRD_START_RESET 0x0 3883 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0) 3885 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001) 3907 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 3913 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 3916 #define ALT_QSPI_INDRD_CANCEL_LSB 1 3918 #define ALT_QSPI_INDRD_CANCEL_MSB 1 3920 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1 3922 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 3924 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd 3926 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0 3928 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1) 3930 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002) 3952 #define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 3958 #define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 3961 #define ALT_QSPI_INDRD_RD_STAT_LSB 2 3963 #define ALT_QSPI_INDRD_RD_STAT_MSB 2 3965 #define ALT_QSPI_INDRD_RD_STAT_WIDTH 1 3967 #define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 3969 #define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb 3971 #define ALT_QSPI_INDRD_RD_STAT_RESET 0x0 3973 #define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2) 3975 #define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004) 3998 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 4004 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 4007 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3 4009 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3 4011 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 4013 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 4015 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 4017 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 4019 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3) 4021 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008) 4043 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 4049 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 4052 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4 4054 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4 4056 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 4058 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 4060 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef 4062 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 4064 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4) 4066 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010) 4089 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 4095 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 4098 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 4100 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 4102 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 4104 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 4106 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf 4108 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 4110 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5) 4112 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020) 4124 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 4126 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 4128 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 4130 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 4132 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f 4134 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 4136 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6) 4138 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0) 4140 #ifndef __ASSEMBLY__ 4154 uint32_t cancel : 1;
4155 const uint32_t rd_status : 1;
4156 uint32_t sram_full : 1;
4157 const uint32_t rd_queued : 1;
4158 uint32_t ind_ops_done_status : 1;
4159 const uint32_t num_ind_ops_done : 2;
4168 #define ALT_QSPI_INDRD_OFST 0x60 4192 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0 4194 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31 4196 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32 4198 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff 4200 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000 4202 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0 4204 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) 4206 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) 4208 #ifndef __ASSEMBLY__ 4221 uint32_t level : 32;
4229 #define ALT_QSPI_INDRDWATER_OFST 0x64 4251 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0 4253 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31 4255 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32 4257 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff 4259 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000 4261 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0 4263 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) 4265 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) 4267 #ifndef __ASSEMBLY__ 4288 #define ALT_QSPI_INDRDSTADDR_OFST 0x68 4310 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0 4312 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31 4314 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32 4316 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff 4318 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000 4320 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0 4322 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) 4324 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) 4326 #ifndef __ASSEMBLY__ 4339 uint32_t value : 32;
4347 #define ALT_QSPI_INDRDCNT_OFST 0x6c 4388 #define ALT_QSPI_INDWR_START_E_END 0x1 4394 #define ALT_QSPI_INDWR_START_E_DISD 0x0 4397 #define ALT_QSPI_INDWR_START_LSB 0 4399 #define ALT_QSPI_INDWR_START_MSB 0 4401 #define ALT_QSPI_INDWR_START_WIDTH 1 4403 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001 4405 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe 4407 #define ALT_QSPI_INDWR_START_RESET 0x0 4409 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0) 4411 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001) 4433 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 4439 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 4442 #define ALT_QSPI_INDWR_CANCEL_LSB 1 4444 #define ALT_QSPI_INDWR_CANCEL_MSB 1 4446 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1 4448 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 4450 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd 4452 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0 4454 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1) 4456 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002) 4478 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 4484 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 4487 #define ALT_QSPI_INDWR_RDSTAT_LSB 2 4489 #define ALT_QSPI_INDWR_RDSTAT_MSB 2 4491 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1 4493 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 4495 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb 4497 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0 4499 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2) 4501 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004) 4510 #define ALT_QSPI_INDWR_SRAMFULL_LSB 3 4512 #define ALT_QSPI_INDWR_SRAMFULL_MSB 3 4514 #define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 4516 #define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 4518 #define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 4520 #define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 4522 #define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3) 4524 #define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008) 4546 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 4552 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 4555 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4 4557 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4 4559 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 4561 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 4563 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef 4565 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 4567 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4) 4569 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010) 4592 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 4598 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 4601 #define ALT_QSPI_INDWR_INDDONE_LSB 5 4603 #define ALT_QSPI_INDWR_INDDONE_MSB 5 4605 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1 4607 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 4609 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf 4611 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0 4613 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5) 4615 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020) 4627 #define ALT_QSPI_INDWR_INDCNT_LSB 6 4629 #define ALT_QSPI_INDWR_INDCNT_MSB 7 4631 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2 4633 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 4635 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f 4637 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0 4639 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6) 4641 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0) 4643 #ifndef __ASSEMBLY__ 4657 uint32_t cancel : 1;
4658 const uint32_t rdstat : 1;
4659 const uint32_t sramfull : 1;
4660 const uint32_t rdqueued : 1;
4661 uint32_t inddone : 1;
4662 const uint32_t indcnt : 2;
4671 #define ALT_QSPI_INDWR_OFST 0x70 4695 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0 4697 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31 4699 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32 4701 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff 4703 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000 4705 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff 4707 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) 4709 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) 4711 #ifndef __ASSEMBLY__ 4724 uint32_t level : 32;
4732 #define ALT_QSPI_INDWRWATER_OFST 0x74 4754 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0 4756 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31 4758 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32 4760 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff 4762 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000 4764 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0 4766 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) 4768 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) 4770 #ifndef __ASSEMBLY__ 4791 #define ALT_QSPI_INDWRSTADDR_OFST 0x78 4813 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0 4815 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31 4817 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32 4819 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff 4821 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000 4823 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0 4825 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) 4827 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) 4829 #ifndef __ASSEMBLY__ 4842 uint32_t value : 32;
4850 #define ALT_QSPI_INDWRCNT_OFST 0x7c 4893 #define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1 4899 #define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0 4902 #define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0 4904 #define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0 4906 #define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1 4908 #define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001 4910 #define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe 4912 #define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0 4914 #define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0) 4916 #define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001) 4938 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1 4944 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0 4947 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1 4949 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1 4951 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1 4953 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002 4955 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd 4957 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0 4959 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1) 4961 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002) 4973 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7 4975 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11 4977 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5 4979 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80 4981 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f 4983 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0 4985 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7) 4987 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80) 5015 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0 5021 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1 5027 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2 5033 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3 5039 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4 5045 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5 5051 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6 5057 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7 5060 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12 5062 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14 5064 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3 5066 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000 5068 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff 5070 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0 5072 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12) 5074 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000) 5097 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1 5103 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0 5106 #define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15 5108 #define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15 5110 #define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1 5112 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000 5114 #define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff 5116 #define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0 5118 #define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15) 5120 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000) 5147 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0 5153 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1 5159 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2 5165 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3 5168 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16 5170 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17 5172 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2 5174 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000 5176 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff 5178 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0 5180 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16) 5182 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000) 5205 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1 5211 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0 5214 #define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18 5216 #define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18 5218 #define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1 5220 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000 5222 #define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff 5224 #define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0 5226 #define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18) 5228 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000) 5251 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1 5257 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0 5260 #define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19 5262 #define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19 5264 #define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1 5266 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000 5268 #define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff 5270 #define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0 5272 #define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19) 5274 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000) 5303 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0 5309 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1 5315 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2 5321 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3 5327 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4 5333 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5 5339 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6 5345 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7 5348 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20 5350 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22 5352 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3 5354 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000 5356 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff 5358 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0 5360 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20) 5362 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000) 5385 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1 5391 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0 5394 #define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23 5396 #define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23 5398 #define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1 5400 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000 5402 #define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff 5404 #define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0 5406 #define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23) 5408 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000) 5429 #define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24 5431 #define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31 5433 #define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8 5435 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000 5437 #define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff 5439 #define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0 5441 #define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24) 5443 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000) 5445 #ifndef __ASSEMBLY__ 5458 uint32_t execcmd : 1;
5459 const uint32_t cmdexecstat : 1;
5461 uint32_t numdummybytes : 5;
5462 uint32_t numwrdatabytes : 3;
5463 uint32_t enwrdata : 1;
5464 uint32_t numaddrbytes : 2;
5465 uint32_t enmodebit : 1;
5466 uint32_t encmdaddr : 1;
5467 uint32_t numrddatabytes : 3;
5468 uint32_t enrddata : 1;
5469 uint32_t cmdopcode : 8;
5477 #define ALT_QSPI_FLSHCMD_OFST 0x90 5501 #define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0 5503 #define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31 5505 #define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32 5507 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff 5509 #define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000 5511 #define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0 5513 #define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) 5515 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) 5517 #ifndef __ASSEMBLY__ 5538 #define ALT_QSPI_FLSHCMDADDR_OFST 0x94 5562 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0 5564 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31 5566 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32 5568 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff 5570 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000 5572 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0 5574 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) 5576 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) 5578 #ifndef __ASSEMBLY__ 5599 #define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0 5625 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0 5627 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31 5629 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32 5631 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff 5633 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000 5635 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0 5637 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) 5639 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) 5641 #ifndef __ASSEMBLY__ 5662 #define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4 5687 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0 5689 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31 5691 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32 5693 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff 5695 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000 5697 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0 5699 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) 5701 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) 5703 #ifndef __ASSEMBLY__ 5724 #define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8 5749 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0 5751 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31 5753 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32 5755 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff 5757 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000 5759 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0 5761 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) 5763 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) 5765 #ifndef __ASSEMBLY__ 5786 #define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac 5806 #define ALT_QSPI_MODULEID_VALUE_LSB 0 5808 #define ALT_QSPI_MODULEID_VALUE_MSB 24 5810 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25 5812 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff 5814 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000 5816 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001 5818 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0) 5820 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff) 5822 #ifndef __ASSEMBLY__ 5835 const uint32_t value : 25;
5844 #define ALT_QSPI_MODULEID_OFST 0xfc 5846 #ifndef __ASSEMBLY__ 5859 volatile ALT_QSPI_CFG_t cfg;
5860 volatile ALT_QSPI_DEVRD_t devrd;
5861 volatile ALT_QSPI_DEVWR_t devwr;
5862 volatile ALT_QSPI_DELAY_t delay;
5863 volatile ALT_QSPI_RDDATACAP_t rddatacap;
5864 volatile ALT_QSPI_DEVSZ_t devsz;
5865 volatile ALT_QSPI_SRAMPART_t srampart;
5866 volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig;
5867 volatile ALT_QSPI_DMAPER_t dmaper;
5868 volatile ALT_QSPI_REMAPADDR_t remapaddr;
5869 volatile ALT_QSPI_MODBIT_t modebit;
5870 volatile ALT_QSPI_SRAMFILL_t sramfill;
5871 volatile ALT_QSPI_TXTHRESH_t txthresh;
5872 volatile ALT_QSPI_RXTHRESH_t rxthresh;
5873 volatile uint32_t _pad_0x38_0x3f[2];
5874 volatile ALT_QSPI_IRQSTAT_t irqstat;
5875 volatile ALT_QSPI_IRQMSK_t irqmask;
5876 volatile uint32_t _pad_0x48_0x4f[2];
5877 volatile ALT_QSPI_LOWWRPROT_t lowwrprot;
5878 volatile ALT_QSPI_UPPWRPROT_t uppwrprot;
5879 volatile ALT_QSPI_WRPROT_t wrprot;
5880 volatile uint32_t _pad_0x5c_0x5f;
5881 volatile ALT_QSPI_INDRD_t indrd;
5882 volatile ALT_QSPI_INDRDWATER_t indrdwater;
5883 volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr;
5884 volatile ALT_QSPI_INDRDCNT_t indrdcnt;
5885 volatile ALT_QSPI_INDWR_t indwr;
5886 volatile ALT_QSPI_INDWRWATER_t indwrwater;
5887 volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr;
5888 volatile ALT_QSPI_INDWRCNT_t indwrcnt;
5889 volatile uint32_t _pad_0x80_0x8f[4];
5890 volatile ALT_QSPI_FLSHCMD_t flashcmd;
5891 volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr;
5892 volatile uint32_t _pad_0x98_0x9f[2];
5893 volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo;
5894 volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup;
5895 volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo;
5896 volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup;
5897 volatile uint32_t _pad_0xb0_0xfb[19];
5898 volatile ALT_QSPI_MODULEID_t moduleid;
5902 typedef volatile struct ALT_QSPI_s ALT_QSPI_t;
5906 volatile uint32_t cfg;
5907 volatile uint32_t devrd;
5908 volatile uint32_t devwr;
5909 volatile uint32_t delay;
5910 volatile uint32_t rddatacap;
5911 volatile uint32_t devsz;
5912 volatile uint32_t srampart;
5913 volatile uint32_t indaddrtrig;
5914 volatile uint32_t dmaper;
5915 volatile uint32_t remapaddr;
5916 volatile uint32_t modebit;
5917 volatile uint32_t sramfill;
5918 volatile uint32_t txthresh;
5919 volatile uint32_t rxthresh;
5920 volatile uint32_t _pad_0x38_0x3f[2];
5921 volatile uint32_t irqstat;
5922 volatile uint32_t irqmask;
5923 volatile uint32_t _pad_0x48_0x4f[2];
5924 volatile uint32_t lowwrprot;
5925 volatile uint32_t uppwrprot;
5926 volatile uint32_t wrprot;
5927 volatile uint32_t _pad_0x5c_0x5f;
5928 volatile uint32_t indrd;
5929 volatile uint32_t indrdwater;
5930 volatile uint32_t indrdstaddr;
5931 volatile uint32_t indrdcnt;
5932 volatile uint32_t indwr;
5933 volatile uint32_t indwrwater;
5934 volatile uint32_t indwrstaddr;
5935 volatile uint32_t indwrcnt;
5936 volatile uint32_t _pad_0x80_0x8f[4];
5937 volatile uint32_t flashcmd;
5938 volatile uint32_t flashcmdaddr;
5939 volatile uint32_t _pad_0x98_0x9f[2];
5940 volatile uint32_t flashcmdrddatalo;
5941 volatile uint32_t flashcmdrddataup;
5942 volatile uint32_t flashcmdwrdatalo;
5943 volatile uint32_t flashcmdwrdataup;
5944 volatile uint32_t _pad_0xb0_0xfb[19];
5945 volatile uint32_t moduleid;
Definition: alt_qspi.h:1433
Definition: alt_qspi.h:3809
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